28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 47
![no-image](/images/manufacturer_photos/0/4/449/mindspeed_technologies_sml.jpg)
28478G-18
Manufacturer Part Number
28478G-18
Description
Multichannel Synchronous Communications Controller 208-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.28478G-18.pdf
(195 pages)
Specifications of 28478G-18
Package
208BGA
Maximum Data Rate
32768 Kbps
Transmission Media Type
Wire
Power Supply Type
Analog
Typical Supply Current
250 mA
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
3 V
Maximum Operating Supply Voltage
3.6 V
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Table 2-4.
28478-DSH-002-E
FOOTNOTE:
Field
15:10
Bit
9
8
7
6
5
4
3
2
1
0
An active-low signal is denoted by a trailing asterisk (*).
Register 1, Address 04h (2 of 2)
Command
Name
Preliminary Information / Mindspeed Proprietary and Confidential
Reset
Value
Mindspeed Technologies
0
0
0
0
0
0
0
0
0
0
0
Type
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
Unused.
Fast back-to-back mode is not supported.
SERR* enable.
If 1, disables MUSYCC’s SERR* driver.
If 0, enables MUSYCC’s SERR* driver and allows reporting of address parity
errors.
Wait cycle control. MUSYCC does not support address stepping.
Parity error response. This bit controls MUSYCC’s Function 0 response to
parity errors.
If 1, MUSYCC takes normal action when a parity error is detected on a cycle
with Function 0 as the target.
If 0, MUSYCC ignores parity errors.
VGA palette snoop. Unused.
Memory write and invalidate. The only write cycle type MUSYCC generates is
memory write.
Special cycles. Unused. MUSYCC ignores all special cycles.
Bus master.
If 1, MUSYCC is permitted to act as bus master.
If 0, MUSYCC is disabled from generating PCI accesses.
Memory space. Access control.
If 1, enables MUSYCC to respond to Function 0 memory space access
cycles.
If 0, disables MUSYCC’s response.
I/O space accesses. MUSYCC does not contain any I/O space registers.
®
Description
Host Interface
34
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