28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 36

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 1-4.
28478-DSH-002-E
117, 122,
125, 128,
131, 136,
140, 143
116, 121,
124, 127,
130, 135,
139, 142
115, 120,
123, 126,
129, 134,
138, 141
4, 8, 12, 18,
22, 26, 32,
208
1, 5, 9, 15,
19, 23, 29,
33
Pin No.
MQFP
CN8478 Hardware Signal Definitions (2 of 6)
TCLK[7:0]
TSYNC[7:0]
TDAT[7:0]
RCLK[7:0]
RSYNC[7:0]
Pin Label
Preliminary Information / Mindspeed Proprietary and Confidential
Transmit Clock
Transmit
Synchronization
Transmit Data
Receive Clock
Receive
Synchronization
Signal Name
Mindspeed Technologies
(1)
(1)
(1)
(1)
t/s O
I/O
I
I
I
I
Controls the rate at which data is transmitted. Synchronizes transitions for
TDATx and sampling of TSYNCx. Valid frequencies from DC to 8.192
±
TSYNC is sampled on the specified active edge of the corresponding
transmit clock, TCLKx. See TSYNC_EDGE bit field in
As TSYNCx signal transitions low-to-high, start of a transmit frame is
indicated. For T1 mode, the corresponding data bit latched out during the
same bit time period (but not necessarily the same clock edge) is the F-bit
of the T1 frame. For E1 modes, the corresponding data bit latched out
during the same bit time period (but not necessarily the same clock edge)
is bit 0 of the E1 frame. For Nx64 mode, the corresponding data bit is
latched out 4-bit time periods later and is bit 0 of the Nx64 frame.
TSYNCx must remain asserted high for a minimum of a setup and hold
time relative to the active clock edge for this signal. If the flywheel
mechanism is used, no other synchronization signal is required, because
MUSYCC tracks the start of each subsequent frame. If the flywheel
mechanism is not used, then a subsequent low-to-high assertion is
required to indicate the start of the next frame. See SFALIGN bit field in
Table
Serial data latched out on active edge of transmit clock, TCLKx. If channel
is unmapped to time slot, data bit is considered invalid and MUSYCC
outputs either three-state signal or logic 1 depending on value of bit field
TRITX in
Active edge samples RDATx and RSYNCx. Valid frequencies from DC to
8.192 ± 10% MHz. Schmitt trigger driver.
RSYNCx is sampled on the specified active edge of the corresponding
receive clock, RCLKx. See RSYNC_EDGE bit field in
As RSYNCx signal transitions low-to-high, start of a receive frame is
indicated. For T1 mode, the corresponding data bit sampled and stored
during the same bit time period (but not necessarily the same clock edge)
is the F-bit of the T1 frame. For E1 modes, the corresponding data bit
sampled and stored during the same bit time period (but not necessarily
the same clock edge) is bit 0 of the E1 frame. For Nx64 mode, the
corresponding data bit sampled and stored during the same bit time
period (but not necessarily the same clock edge) is bit 0 of the Nx64
frame.
RSYNCx must be asserted high for a minimum of a setup and hold time
relative to the active clock edge for this signal. If the flywheel mechanism
is used, no other synchronization signal is required, because MUSYCC
tracks the start of each subsequent frame. If the flywheel mechanism is
not used, a subsequent low-to-high assertion is required to indicate the
start of the next frame. See SFALIGN bit field in
10% MHz. Schmitt trigger driver.
5-10.
Table
®
5-12.
Definition
Table
Table
Table
5-10.
5-12.
5-12.
23