28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 78

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

The following port mappings are available:
•
•
•
Mapping a serial port to one or more logical channels in a channel group is one element of serial port configuration;
another is indicating the channelized data rate of the serial interface, accomplished by configuring the PORTMAP
bit field
layer interface indicates the relationship to physical layer time slots.
Each serial port can be configured to support 24, 32, 64, 128 or a variable number of 8-bit time slots up to 128.
Each serial port can be configured to support data rates up to and including 8.192 Mbps. Also, each serial port can
be independently wired to a separate source of serial data, or all four serial ports can be wired to a single source of
serial data.
4.7
Each channel group contains a separate internal buffer memory space for transmit and receive operations. Within
each of these spaces, separate areas are set aside for specific functions.
Each channel within the group must be allocated buffer space before the channel can be activated.
the internal buffer memory allocation. This space acts as a holding buffer for incoming (Rx) and outgoing (Tx) data.
Data buffers for each channel are allocated using the BUFFLOC and BUFFLEN bit fields
Configuration
available FIFO services the serial interface, and the other half services data in shared memory.
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allocated to a direction of the channel.
Table 4-2.
28478-DSH-002-E
Fixed Data Buffer
Subchannel Map
(or Additional Data Buffer if No Subchanneling)
Time Slot Map
Total
illustrate the receive and transmit data flows, respectively. BUFFLEN+1 specifies half the size of the buffer space
PORTMAP = 0, 1x port mode
Default mode after device reset. Each serial port is logically connected to one channel group, and each port
terminates up to 32 bidirectional channels.
PORTMAP = 1, 2x port mode
Each of two serial ports is logically connected to two channel groups. In this mode, serial port 0 is connected to
channel groups 0 and 1, serial port 1 is connected to channel groups 2 and 3, serial port 2 is connected to
channel group 4 and 5, and serial port 3 is connected to channel group 6 and 7. Each serial port terminates up
to 64 bidirectional channels.
PORTMAP = 2, 4x port mode
Serial port 0 is logically connected to channel groups 0, 1, 2, and 3, and serial port 1 is logically connected to
channel groups 4, 5, 6, and 7. Serial ports 2 through 7 are disabled.
(Table 5-6, Global Configuration
Internal Buffer Memory Layout
Descriptor). Both receiver and transmitter of a channel use a data buffer scheme where half the
Tx and Rx FIFO Buffer Allocation and Management
Memory Area
Preliminary Information / Mindspeed Proprietary and Confidential
Mindspeed Technologies
Descriptor). The connection between the serial port and the physical
®
160 dwords
64 dwords
64 dwords
32 dwords
Transmit
640 bytes
(Table 5-18, Channel
Figures 4-6
Serial Interface
160 dwords
64 dwords
64 dwords
32 dwords
640 bytes
Receive
Table 4-2
and
lists
4-
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