C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 120

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
13.5.2. Non-multiplexed Configuration
In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a
Non-multiplexed Configuration is shown in Figure 13.3. See
page 124
13.6. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 13.4, based on
the EMIF Mode bits in the EMI0CF register (SFR Definition 13.2). These modes are summarized below.
More information about the different modes can be found in
120
EMI0CF[3:2] = 00
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
E
M
I
F
for more information about Non-multiplexed operation.
A[15:0]
D[7:0]
WR
RD
Figure 13.3. Non-multiplexed Configuration Example
0xFFFF
0x0000
EMI0CF[3:2] = 01
(No Bank Select)
On-Chip XRAM
Figure 13.4. EMIF Operating Modes
Off-Chip
Memory
ADDRESS BUS
DATA BUS
0xFFFF
0x0000
Rev. 1.3
(Optional)
EMI0CF[3:2] = 10
On-Chip XRAM
(Bank Select)
Off-Chip
Memory
Section “13.7.1. Non-multiplexed Mode” on
Section “13.7. Timing” on page
V
DD
8
0xFFFF
0x0000
EMI0CF[3:2] = 11
A[15:0]
I/O[7:0]
CE
WE
OE
Off-Chip
Memory
64K X 8
SRAM
122.
0xFFFF
0x0000