C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 73

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

9.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in
in
Special Function Register (SFR) address space
tion
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
Section
- Fully Compatible with MCS-51 Instruction
- 0 to 48 MHz Clock Frequency
- 256 Bytes of Internal RAM
- 25 Port I/O
15). The CIP-51 also includes on-chip debug hardware (see description in
CIP-51 Microcontroller
Set
18), an Enhanced SPI (see description in
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
PROGRAM COUNTER (PC)
CONTROL
Figure 9.1. CIP-51 Block Diagram
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
Section
ALU
(Section
Rev. 1.3
TMP2
DATA BUS
DATA BUS
D8
D8
D8
21), an enhanced full-duplex UART (see description
Section
A16
D8
D8
D8
D8
9.2.6), and 25 Port I/O (see description in
B REGISTER
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
REGISTER
INTERRUPT
ADDRESS
INTERFACE
INTERFACE
INTERFACE
MEMORY
SRAM
20), 256 bytes of internal RAM, 128 byte
SFR
BUS
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
Section
23), and interfaces
Sec-
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