C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 197

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

ARBLOST
TXMODE
MASTER
ACKRQ
STO
ACK
STA
Bit
SI
• A START is generated.
• START is generated.
• SMB0DAT is written before the start of an
• A START followed by an address byte is
• A STOP is detected while addressed as a
• Arbitration is lost due to a detected STOP.
• A byte has been received and an ACK
• A repeated START is detected as a MASTER
• SCL is sensed low while attempting to gener-
• SDA is sensed low while transmitting a ‘1’
• The incoming ACK value is low (ACKNOWL-
• A START has been generated.
• Lost arbitration.
• A byte has been transmitted and an ACK/
• A byte has been received.
• A START or repeated START followed by a
• A STOP has been received.
Table 17.3. Sources for Hardware Changes to SMB0CN
SMBus frame.
received.
slave.
response value is needed.
when STA is low (unwanted repeated START).
ate a STOP or repeated START condition.
(excluding ACK bits).
EDGE).
NACK received.
slave address + R/W has been received.
Set by Hardware When:
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Rev. 1.3
• A STOP is generated.
• Arbitration is lost.
• A START is detected.
• Arbitration is lost.
• SMB0DAT is not written before the
• Must be cleared by software.
• A pending STOP is generated.
• After each ACK cycle.
• Each time SI is cleared.
• The incoming ACK value is high (NOT
• Must be cleared by software.
start of an SMBus frame.
ACKNOWLEDGE).
Cleared by Hardware When:
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