C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 241
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C8051F340-GQR
Manufacturer Part Number
C8051F340-GQR
Description
MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F340-GQR.pdf
(276 pages)
Specifications of C8051F340-GQR
Package
48TQFP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
40
Interface Type
I2C/SMBus/SPI/UART/USB
On-chip Adc
17-chx10-bit
Number Of Timers
4
Ram Size
4.25 KB
Program Memory Size
64 KB
Program Memory Type
Flash
Operating Temperature
-40 to 85 °C
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Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0: SCA1-SCA0: Timer 0/1 Prescale Bits.
T3MH
R/W
Bit7
T3MH: Timer 3 High Byte Clock Select.
This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split
8-bit timer mode. T3MH is ignored if Timer 3 is in any other mode.
0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 high byte uses the system clock.
T3ML: Timer 3 Low Byte Clock Select.
This bit selects the clock supplied to Timer 3. If Timer 3 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.
1: Timer 3 low byte uses the system clock.
T2MH: Timer 2 High Byte Clock Select.
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split
8-bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
T2ML: Timer 2 Low Byte Clock Select.
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
Note: External clock divided by 8 is synchronized with the
SCA1
T3ML
0
0
1
1
R/W
Bit6
system clock.
SCA0
SFR Definition 21.3. CKCON: Clock Control
0
1
0
1
T2MH
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
System clock divided by 12
System clock divided by 48
External clock divided by 8
System clock divided by 4
T2ML
R/W
Bit4
Prescaled Clock
Rev. 1.3
T1M
R/W
Bit3
T0M
R/W
Bit2
SCA1
R/W
Bit1
SCA0
R/W
Bit0
SFR Address:
00000000
Reset Value
0x8E
241
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