C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 168

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
16.5.2. FIFO Double Buffering
FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum
packet size is halved and the FIFO may contain two packets at a time. This mode is available for
Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN
Endpoint and/or the OUT endpoint. When Split Mode is not enabled, double-buffering may be enabled for
the entire endpoint FIFO. See Table 16.3 for a list of maximum packet sizes for each FIFO configuration.
16.5.1. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.
168
Endpoint
Number
R/W
Bit7
0
1
2
3
USB Register Definition 16.6. FIFOn: USB0 Endpoint FIFO Access
USB Addresses 0x20–0x23 provide access to the 4 pairs of endpoint FIFOs:
Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint.
Reading from the FIFO address unloads data from the OUT FIFO for the corresponding
endpoint.
IN/OUT Endpoint FIFO
R/W
Bit6
Split Mode
Enabled?
N/A
N
Y
N
Y
N
Y
0
1
2
3
R/W
Bit5
Table 16.3. FIFO Configurations
Maximum IN Packet Size (Dou-
ble Buffer Disabled / Enabled)
R/W
Bit4
FIFODATA
USB Address
0x20
0x21
0x22
0x23
256 / 128
128 / 64
Rev. 1.3
64 / 32
R/W
Bit3
R/W
Bit2
256 / 128
512 / 256
128 / 64
64
R/W
Bit1
Maximum OUT Packet Size
(Double Buffer Disabled /
Enabled)
256 / 128
128 / 64
64 / 32
R/W
Bit0
0x20 - 0x23
USB Address:
00000000
Reset Value