C8051F340-GQR Silicon Laboratories Inc, C8051F340-GQR Datasheet - Page 265

• Manufacturer Part Number: C8051F340-GQR
• Description: MCU 8-Bit C8051F34x 8051 CISC 64KB Flash 3.3V/5V 48-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F340-GQR

• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 40
• Interface Type: I2C/SMBus/SPI/UART/USB
• On-chip Adc: 17-chx10-bit
• Number Of Timers: 4
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Operating Temperature: -40 to 85 °C

The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and
PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF4 flag (PCA0CN.4) while the WDT is
enabled.
22.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL4 defaults to 0x00. Using Equation 22.4, this results in a WDT
timeout interval of 256 PCA clocks. Table 22.3 lists some example timeout intervals for typical system
clocks.
1. Disable the WDT by writing a ‘0’ to the WDTE bit.
2. Select the desired PCA clock source (with the CPS2-CPS0 bits).
3. Load PCA0CPL4 with the desired WDT update offset value.
4. Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in
5. Enable the WDT by setting the WDTE bit to ‘1’.
6. (optional) Lock the WDT (prevent WDT disable until the next system reset) by setting the
7. Write a value to PCA0CPH4 to reload the WDT. 
Idle mode).
WDLCK bit to ‘1’.
Equation 22.4. Watchdog Timer Offset in PCA Clocks
Notes:
System Clock (Hz)
1. Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L
2. System Clock reset frequency.
Table 22.3. Watchdog Timer Timeout Intervals
Offset
12,000,000
12,000,000
12,000,000
24,000,000
24,000,000
24,000,000
1,500,000
1,500,000
1,500,000
value of 0x00 at the update time.
32,768
32,768
32,768
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
=
2
2
2

256 PCA0CPL4

PCA0CPL4
Rev. 1.3
255
128
255
128
255
128
255
128
32
32
32
32

+

256 PCA0L
Timeout Interval (ms)
–
12,093.75
3,093.75
24,000
524.3
264.2
65.5
33.0
32.8
16.5
67.6
8.4
4.2

1
265