DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 135

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

VSUPPLY[1:0]
9.3.7
Read: anytime
Write: anytime. It is recommended that BRATE[1:0] and BLKMODE, must not be modified while BLINK
is asserted.
Freescale Semiconductor
CPCADJ[1:0]
HDRVBUF
BBYPASS
Reset
Field
5:4
1:0
3
2
W
R
BLINK
LCD Blink Control Register (LCDBCTL)
0
7
LCD Module Charge Pump Clock Adjust- Adjust the clock source for the charge pump
00 Configures for 2728 Hz charge pump frequency (LCDCLK = 32.768khz)
01 Configures for 1364 Hz charge pump frequency (LCDCLK = 32.768khz)
10 Configures for 682 Hz charge pump frequency (LCDCLK = 32.768khz)
11 Configures for 341 Hz charge pump frequency (LCDCLK = 32.768khz)
High Drive Buffer Mode Select — This bit enhances the VLCD buffer drive active high buffer drive for larger
capacitance LCD glass. (See
0 Normal buffer drive. (Ideal for 2000 pF LCD glass.)
1 High buffer drive. (Ideal for 4000 pF LCD glass.)
Op Amp Control— Determines whether the internal LCD op amp buffer is bypassed. (See
details)
0 Buffered mode
1 Unbuffered mode
Voltage Supply Control— Configures whether the LCD module power supply is external or internal. It is
recommended that this bit field not be modified while the LCD module is enabled (e.g., LCDEN = 1). See
Figure 9-17
Unimplemented or Reserved
for more detail.
Table 9-10. LCDSUPPLY Field Descriptions (continued)
0
0
6
Figure 9-8. LCD Blink Control Register (LCDBCTL)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Charge Pump Clock Rate
0
0
5
Figure 9-17
for details.)
0
0
4
=
Description
LCDCLK / (6
BLKMODE
3
0
Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
×
2
(C
PADJ[1:0] +1)
BRATE2
0
2
)
BRATE1
0
1
Figure 9-17
BRATE0
Eqn. 9-3
0
0
for
135