DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 269

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

15.1.1.6 Low-Power Mode Operation
The ADC is capable of running in stop3 mode but requires LVDSE in SPMSC1 to be set.
Freescale Semiconductor
BP3/FP40
FP[39:0]
V
V
V
V
BP[2:0]
DDAD
SSAD
REFH
V
V
REFL
V
CAP1
CAP2
V
V
V
V
V
LCD
LL1
LL2
LL3
DD
SS
Figure 15-1. MC9S08LC60 Series Block Diagram Highlighting ADC Block and Pins
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
LOW-POWER OSCILLATOR
MODES OF OPERATION
(LC36 = 24,576 BYTES)
(LC36 = 12,288 BYTES)
(LC60 = 32,768 BYTES)
(LC60 = 28,464 BYTES)
(LC36 = 2560 BYTES)
(LC60 = 4096 BYTES)
POWER MANAGEMENT
BKGD
CPU
IRQ
RTI
GENERATOR (ICG)
INTERNAL CLOCK
LIQUID CRYSTAL
DISPLAY DRIVER
USER FLASH A
USER FLASH B
HCS08 CORE
USER RAM
REGULATOR
VOLTAGE
LCD
COP
BKP
INT
LVD
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
NOTES:
SERIAL COMMUNICATIONS
2-CHANNEL TIMER/PWM
DEBUG MODULE (DBG)
2-CHANNEL TIMER/PWM
ANALOG COMPARATOR
1. Port pins are software configurable with pullup device if input port.
2. Pin contains software configurable pullup/pulldown device if IRQ enabled
3. IRQ does not have a clamp diode to V
4. Pin contains integrated pullup device.
5. Input-only RESET is shared with output-only PTB2. Default function after reset is
6. IRQ is shared with PTC7/KBI2P7/TPMCLK. Default function after reset is
7. PTC6/BKGD/MS is an output only pin
8. FP[39:32], PTA[1:0], and PTA[7:4] are not available in the 64 LQFP.
9. ACMPO is not available.
ANALOG-TO-DIGITAL
SERIAL PERIPHERAL
SERIAL PERIPHERAL
CONVERTER (ADC)
INTERRUPT (KBI1)
INTERRUPT (KBI2)
INTERFACE (SPI1)
INTERFACE (SPI2)
8-BIT KEYBOARD
8-BIT KEYBOARD
INTERFACE (SCI)
IIC MODULE (IIC)
(IRQPE = 1).
RESET.
output-only PTC7.
ON-CHIP ICE
(ACMP)
(TPM2)
(TPM1)
12-BIT
Chapter 15 Analog-to-Digital Converter (S08ADC12V1)
TPMCLK
RxD
SS1
SPSCK1
MOSI1
SCL
SDA
SS2
SPSCK2
MOSI2
MISO2
TxD
MISO1
ACMP–
ACMP+
4
8
5
3
TPM1CH0
TPM1CH1
XTAL
EXTAL
ADP[7:4]
ADP3
ADP2
ADP1
ADP0
TPM2CH1
TPM2CH0
RESET
IRQ
DD
. IRQ should not be driven above V
PTA[7:4]/KBI1P[7:4]/ADP[7:4]
PTA3/KBI1P3/ADP3/ACMP–
PTA2/KBI1P2/ADP2/ACMP+
PTA[1:0]/KBI1P[1:0]/ADP[1:0]
PTB7/KBI2P4/SS1
PTB6/KBI2P3/SPSCK1
PTB5/MOSI1/SCL
PTB4/MISO1/SDA
PTB3/KBI2P2
PTB2/RESET
PTB1/KBI2P1/XTAL
PTB0/KBI2P0/EXTAL
PTC7/KBI2P7/IRQ/TPMCLK
PTC6/BKGD/MS
PTC5/KBI2P6/TPM2CH1
PTC4/KBI2P5/TPM2CH0
PTC3/SS2/TPM1CH1
PTC2/SPSCK2/TPM1CH0
PTC1/MOSI2/TxD
PTC0/MISO2/RxD
269
DD
.