DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 45

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DEMO9S08LIN

Manufacturer Part Number
DEMO9S08LIN
Description
Manufacturer
Freescale
Datasheet

Specifications of DEMO9S08LIN

Lead Free Status / RoHS Status
Compliant
0x1800
0x1801
0x1802
0x1803
0x1804
0x1805
0x1806
0x1807
0x1808
0x1809
0x180A
0x180B
0x180C
0x180D–
0x180F
0x1810
0x1811
0x1812
0x1813
0x1814
0x1815
0x1816
0x1817
0x1818
0x1819–
0x181F
0x1820
0x1821
0x1822
0x1823
Address Register Name
1
0x0054
0x0055
0x0056
0x0057
0x0058
0x0059
0x005A
0x005B–
0x005F
High-page registers, shown in
so they have been located outside the direct addressable memory space, starting at 0x1800.
Freescale Semiconductor
Address
For the MC9S08LC60 Series, the AMCPO pin is not available, so the ACOPE bit in the ACMPSC register is reserved and does
not have any effect.
SRS
SBDFR
SOPT1
SOPT2
Reserved
Reserved
SDIDH
SDIDL
SRTISC
SPMSC1
SPMSC2
Reserved
SPMSC3
Reserved
DBGCAH
DBGCAL
DBGCBH
DBGCBL
DBGFH
DBGFL
DBGC
DBGT
DBGS
Reserved
FCDIV
FOPT
Reserved
FCNFG
TPM2MODL
TPM2C0SC
TPM2C0VH
TPM2C0VL
TPM2C1SC
TPM2C1VH
TPM2C1VL
Reserved
Register Name
COPCLKS
TRGSEL
DBGEN
KEYEN
DIVLD
COPE
LVWF
REV3
Bit 15
Bit 15
Bit 15
LVDF
Bit 7
POR
RTIF
Bit 7
Bit 7
Bit 7
ID7
AF
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
0
0
0
CH0F
Bit 15
CH1F
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Table
Table 4-3. High-Page Register Summary
FNORED
LVWACK
LVDACK
RTIACK
PRDIV8
BEGIN
COPT
REV2
ARM
PIN
ID6
BF
14
14
14
4-3, are accessed much less often than other I/O and control registers
CH0IE
CH1IE
6
0
0
0
6
6
6
0
14
14
6
6
6
6
RTICLKS
KEYACC
STOPE
LVDIE
ARMF
REV1
LVDV
COP
DIV5
TAG
ID5
13
13
13
MS0B
MS1B
5
0
0
0
5
5
5
0
0
13
13
5
5
5
5
BRKEN
LVDRE
LVWV
REV0
ILOP
RTIE
DIV4
PDF
MS0A
MS1A
ID4
12
12
12
4
0
0
4
4
4
0
0
0
0
12
12
4
4
4
4
LVDSE
PPDF
TRG3
CNT3
ELS0B
ELS1B
RWA
ID11
DIV3
ID3
11
11
11
3
0
0
0
0
0
0
3
3
3
0
0
11
11
3
3
3
3
PPDACK
RWAEN
ELS0A
ELS1A
RTIS2
TRG2
LVDE
CNT2
ID10
DIV2
ICG
ID2
10
10
10
10
10
2
0
0
0
0
2
2
2
0
0
2
2
2
2
BKGDPE
SEC01
RTIS1
TRG1
CNT1
RWB
PDC
DIV1
LVD
ID9
ID1
1
1
0
9
1
0
9
1
1
0
0
0
0
9
1
9
1
9
1
0
Chapter 4 Memory
RWBEN
RSTPE
SEC00
Bit 0
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
RTIS0
BGBE
PPDC
BDFR
TRG0
CNT0
ACIC
Bit 0
DIV0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
0
0
ID8
ID0
0
0
0
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