LAN9210-ABZJ Standard Microsystems (SMSC), LAN9210-ABZJ Datasheet - Page 133
LAN9210-ABZJ
Manufacturer Part Number
LAN9210-ABZJ
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.LAN9210-ABZJ.pdf
(147 pages)
Specifications of LAN9210-ABZJ
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Compliant
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Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9210
6.6
SYMBOL
t
cycle
t
t
t
t
t
t
csh
asu
dsu
csl
ah
dh
nCS, nWR
Data Bus
A[7:1]
PIO writes are used for all LAN9210 write cycles. PIO writes can be performed using Chip Select (nCS)
or Write Enable (nWR). Either or both of these control signals must go high between cycles for the
period specified.
Note: The “Data Bus” width is 16 bits.
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either
PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Deassertion Time (see Note below)
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
nCS, nWR Assertion Time
or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
Parameters t
csh
and t
Figure 6.5 PIO Write Cycle Timing
Table 6.7 PIO Write Cycle Timing
csl
must be extended using wait states to meet the t
DATASHEET
133
MIN
165
32
13
0
7
0
0
TYP
133
cycle
MAX
Revision 2.7 (03-15-10)
minimum.
UNITS
ns
ns
ns
ns
ns
ns
ns
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