LAN9210-ABZJ Standard Microsystems (SMSC), LAN9210-ABZJ Datasheet - Page 62

• Manufacturer Part Number: LAN9210-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9210-ABZJ

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Revision 2.7 (03-15-10)
3.13.1.1
3.13.1.2
Receive Data FIFO Fast Forward
The RX data path implements an automatic data discard function. Using the RX data FIFO Fast
Forward bit (RX_FFWD) in the RX_DP_CTRL register, the host can instruct the LAN9210 to skip the
packet at the head of the RX data FIFO. The RX data FIFO pointers are automatically incremented to
the beginning of the next RX packet.
When performing a fast-forward, there must be at least 4 DWORDs of data in the RX data FIFO for
the packet being discarded. For less than 4 DWORDs do not use RX_FFWD. In this case data must
be read from the RX data FIFO and discarded using standard PIO read operations.
After initiating a fast-forward operation, do not perform any reads of the RX data FIFO, RX status FIFO,
or the TX status FIFO until the RX_FFWD bit is cleared. Other resources can be accessed during this
time (i.e., any registers and/or the TX data FIFO). After the fast-forward operation has completed and
the RX_FFWD bit has been cleared, a wait time restriction must be observed before reading the TX
or RX status FIFO’s, as specified in
on page
FIFO.
The receiver does not have to be stopped to perform a fast-forward operation.
Force Receiver Discard (Receiver Dump)
In addition to the Receive data Fast Forward feature, LAN9210 also implements a receiver "dump"
feature. This feature allows the host processor to flush the entire contents of the RX data and RX
status FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be
returned to their reset state. To perform a receiver dump, the LAN9210 receiver must be halted. Once
the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register. The
RX_DUMP bit is cleared when the dump is complete. For more information on stopping the receiver,
please refer to
on the RX_DUMP bit, please refer to
page
85.
128. Also note that the RX_FFWD will only fast-forward the RX data FIFO, not the RX status
Section 3.13.4, "Stopping and Starting the Receiver," on page
DATASHEET
Section 6.1.2, "Special Restrictions on Back-to-Back Read Cycles,"
Section 5.3.7, "RX_CFG—Receive Configuration Register," on
62
Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
65. For more information
SMSC LAN9210
Datasheet