LAN9210-ABZJ Standard Microsystems (SMSC), LAN9210-ABZJ Datasheet - Page 147

• Manufacturer Part Number: LAN9210-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9210-ABZJ

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9210
REVISION LEVEL & DATE
(05-13-08)
(10-22-07)
(04-11-08)
Rev. 1.92
Rev. 2.1
Rev. 2.0
Table 9.1 Customer Revision History (continued)
Auto-negotiation
Advertisement on page 119
Section 3.5, "Wake-up
Frame Detection," on
page 25
"MAC_CR—MAC Control
Register," on page 105
Section 5.4.12,
"WUCSR—Wake-up Control
and Status Register," on
page 114
Section 3.6.1.1, "RX
Checksum Calculation," on
page 31
Table 7.3 on page 140
Section 1.1, "Block
Diagram"
Section 7.6, "DC Electrical
Specifications," on page 141
Chapter 2 Pin Description
and Configurationon
page 14
Transmit Checksum Offload
Engine (TXCOE) section of
Chapter 3, "Functional
Description," on page
EECLK pin description in
Chapter 2 Pin Description
and Configurationon
page 14
SECTION/FIGURE/ENTRY
and
Section 5.4.1,
DATASHEET
21.
147
Fixed definition of bits 11:10 when equal to “11” by
adding “advertise support for..” to beginning of
definition. Also added note stating “When both
symmetric PAUSE and asymmetric PAUSE
support are advertised, the device will only be
configured to, at most, one of the two settings
upon auto-negotiation completion.”
Added note: “When wake-up frame detection is
enabled via the WUEN bit of the
up Control and Status
up frame will wake-up the device despite the state
of the Disable Broadcast Frame (BCAST) bit in the
MAC_CR—MAC Control
Fixed typo in bit 9: “... Mac Address [1:0] bit set to
0.” was changed to “...Mac Address [0] bit set to 0.”
“checksum = [B0, B1] + C0 + [B2, B3] + C1 + …
+ [0, BN] + CN-1” changed to “checksum = [B1,
B0] + C0 + [B3, B2] + C1 + … + [0, BN] + CN-1”
Added 1.8V Analog Supply Current (VDD_A18)
into the VDD_IO supply current and removed the
1.8V row.
Removed the system memory block and arrow
above the microprocessor/ microcontroller
Input leakage current values added
Pin assignment information re-organized into
separate table.
Note added indicating the proper usage of the TX
checksum preamble (DWORD alignment).
Note added to EECLK pin description to indicate
proper usage.
CORRECTION
Register, a broadcast wake-
Register.”
WUCSR—Wake-
Revision 2.7 (03-15-10)