LAN9210-ABZJ Standard Microsystems (SMSC), LAN9210-ABZJ Datasheet - Page 52

• Manufacturer Part Number: LAN9210-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9210-ABZJ

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Compliant

Revision 2.7 (03-15-10)
3.12.3
3.12.3.1
31:16
BITS
10:0
15
14
13
12
11
Data Start Offset [1:0]:
First TX Data Byte:
TX COMMAND ‘B’
TX Data Format
The TX data section begins at the third DWORD in the TX buffer (after TX command ‘A’ and TX
command ‘B’). The location of the first byte of valid buffer data to be transmitted is specified in the
“Data Start Offset” field of the TX command ‘A’ word.
correlation between the setting of the LSB’s in the “Data Start Offset” field and the byte location of the
first valid data byte. Additionally, transmit buffer data can be offset by up to 7 additional DWORDS as
indicated by the upper three MSB’s (5:2) in the “Data Start Offset” field.
TX data is contiguous until the end of the buffer. The buffer may end on a byte boundary. Unused
bytes at the end of the packet will not be sent to the MIL for transmission.
The Buffer End Alignment field in TX command ‘A’ specifies the alignment that must be maintained for
the associated buffer. End alignment may be specified as 4-, 16-, or 32-byte. The host processor is
responsible for adding the additional data to the end of the buffer. The hardware will automatically
remove this extra data.
TX Buffer Fragmentation Rules
Transmit buffers must adhere to the following rules:
Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to
the corresponding TX status word and can be used by the host to correlate TX status words with
their corresponding packets.
Note:
Reserved. This bit is reserved. Always write zeros to this bit to guarantee future compatibility.
TX Checksum Enable (CK). When this bit is set in conjunction with the first segment (FS) bit in TX
Command ‘A’ and the TX checksum offload engine enable bit (TXCOE_EN) in the
COE_CR—Checksum Offload Engine Control
will calculate a L3 checksum for the associated frame.
Add CRC Disable. When set, the automatic addition of the CRC is disabled.
Disable Ethernet Frame Padding. When set, this bit prevents the automatic addition of padding to
an Ethernet frame of less than 64 bytes. The CRC field is also added despite the state of the Add
CRC Disable field.
Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility.
Packet Length (bytes). This field indicates the total number of bytes in the current packet. This
length does not include the offset or padding. If the Packet Length field does not match the actual
number of bytes in the packet the Transmitter Error (TXE) flag will be set.
Each buffer can start and end on any arbitrary byte alignment
The first buffer of any transmit packet can be any length
The use of packet tags is not required by the hardware. This field can be used by the LAN
software driver for any application. Packet Tags is one application example.
Table 3.13 TX Command 'B' Format
D[31:24]
Table 3.14 TX DATA Start Offset
11
DATASHEET
DESCRIPTION
52
Register, the TX checksum offload engine (TXCOE)
D[23:16]
Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
10
Table 3.14, "TX DATA Start
D[15:8]
01
Offset", shows the
SMSC LAN9210
D[7:0]
00
Datasheet