GD82559ER 824184 Intel, GD82559ER 824184 Datasheet - Page 3

• Manufacturer Part Number: GD82559ER 824184
• Manufacturer: Intel

Specifications of GD82559ER 824184

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

1.
2.
3.
4.
5.
6.
Datasheet
INTRODUCTION ............................................................................................................................. 1
GD82559ER ARCHITECTURAL OVERVIEW ................................................................................ 3
SIGNAL DESCRIPTIONS ............................................................................................................... 7
GD82559ER MEDIA ACCESS CONTROL FUNCTIONAL DESCRIPTION .................................13
GD82559ER TEST PORT FUNCTIONALITY ...............................................................................33
GD82559ER PHYSICAL LAYER FUNCTIONAL DESCRIPTION ................................................37
1.1
1.2
2.1
2.2
2.3
2.4
3.1
3.2
3.3
3.4
3.5
4.1
4.2
4.3
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
5.6
6.1
GD82559ER Overview ....................................................................................................... 1
Suggested Reading ............................................................................................................ 1
Parallel Subsystem Overview ............................................................................................. 3
FIFO Subsystem Overview.................................................................................................4
10/100 Mbps Serial CSMA/CD Unit Overview.................................................................... 5
10/100 Mbps Physical Layer Unit ....................................................................................... 5
Signal Type Definitions ....................................................................................................... 7
PCI Bus Interface Signals................................................................................................... 7
Local Memory Interface Signals ......................................................................................... 9
Testability Port Signals .....................................................................................................10
PHY Signals .....................................................................................................................11
82559ER Initialization .......................................................................................................13
PCI Interface.....................................................................................................................14
Parallel Flash Interface .....................................................................................................28
Serial EEPROM Interface .................................................................................................28
10/100 Mbps CSMA/CD Unit ............................................................................................30
Media Independent Interface (MII) Management Interface...............................................32
Introduction .......................................................................................................................33
Asynchronous Test Mode .................................................................................................33
Test Function Description .................................................................................................33
85/85.................................................................................................................................33
TriState .............................................................................................................................34
Nand - Tree ......................................................................................................................34
100BASE-TX PHY Unit ....................................................................................................37
3.2.1
3.2.2
3.2.3
4.1.1
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.5.1
4.5.2
4.5.3
4.5.4
6.1.1
Address and Data Signals .................................................................................. 7
Interface Control Signals ....................................................................................8
System and Power Management Signals........................................................... 9
Initialization Effects on 82559ER Units ............................................................13
82559ER Bus Operations.................................................................................14
Clockrun Signal ................................................................................................22
Power Management Event Signal ....................................................................22
Power States ....................................................................................................23
Wake-up Events ...............................................................................................27
Full Duplex .......................................................................................................31
Flow Control .....................................................................................................31
Address Filtering Modifications.........................................................................31
Long Frame Reception .....................................................................................31
100BASE-TX Transmit Clock Generation ........................................................37
Networking Silicon — GD82559ER
Contents
iii