GD82559ER 824184 Intel, GD82559ER 824184 Datasheet - Page 31

• Manufacturer Part Number: GD82559ER 824184
• Manufacturer: Intel

Specifications of GD82559ER 824184

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

4.2.4.6
4.2.4.7
Datasheet
.
Auxiliary Power Signal
The 82559ER senses whether it is connected to the PCI power supply or to an auxiliary power
supply (V
FLA1) is sampled when the PCI RST# or ALTRST# signals are active. An external pull-up resistor
should be connected to the 82559ER if it is fed by V
should be left floating. The presence of AUXPWR affects the value reported in the Power
Management Capability Register (PCI Configuration Space, offset DEH). The Power Management
Capability Register is described in more detail in
Register” on page
Alternate Reset Signal
The 82559ER’s ALTRST# input pin functions as a power-on reset input. Following ALTRST#
being driven low, the 82559ER is initialized to a known state. In systems that support auxiliary
power, this pin should be connected to the auxiliary power’s power stable signal (power good) of
the 82559ER’s power source. In a LAN on Motherboard solution, this signal is available on the
system. In network adapter implementations, an external analog device connected to the auxiliary
power supply can be used to produce this signal. In systems that do not have an auxiliary power
source, the ALTRST# signal should be tied to a pull-up resistor.
4.2.4.7.1 Isolate Signal
When the 82559ER is connected to V
In this case, the 82559ER isolates itself from the PCI bus. The 82559ER has a dedicated
ISOLATE# pin that should be connected to the PCI power source’s stable power signal (power
good). Whenever the PCI Bus is in the B3 state, the PCI power good signal becomes inactive and
the 82559ER isolates itself from the PCI bus. During this state, the 82559ER ignores all PCI
signals including the RST# and CLK signals. It also tri-states all PCI outputs, except the PME#
signal. In the transition to an active PCI power state (in other words, from B3 power state to B0
power state), the PCI power good signal shifts high.
AUX
) via the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed with
D0u
D0a
D1
D2
D3 (with power)
Dx (x>0 without
PME#)
Power State
54.
Don’t care
Valid
Invalid
Valid
Invalid
Valid
Invalid
Valid
Invalid
Don’t Care
Link
AUX
, it may be powered on while the PCI bus is powered off.
•
•
Full functionality at full power and wake on invalid
link
Full functionality at full power and wake on valid link
•
•
•
•
Same functionality as D1 (link valid)
Detection for valid link and no link integrity
Same functionality as D1 (link valid)
Detection for valid link and no link integrity
No wake-up functionality
Power-up state
PCI slave access
Wake-up on “interesting” packets and link
invalid
PCI configuration access
Wake on link valid
PCI configuration access
Section 7.1.18, “Power Management Capabilities
AUX
; otherwise, the FLA1/AUXPWR pin
82559ER Functionality
Networking Silicon — GD82559ER
25