GD82559ER 824184 Intel, GD82559ER 824184 Datasheet - Page 60

• Manufacturer Part Number: GD82559ER 824184
• Manufacturer: Intel

Specifications of GD82559ER 824184

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

GD82559ER — Networking Silicon
7.1.13
7.1.14
7.1.15
7.1.16
7.1.17
7.1.18
54
Interrupt Pin Register
The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins,
INTA# through INTD#, a PCI device is connected to. The 82559ER is connected the INTA# pin.
Minimum Grant Register
The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not
applicable to non-master devices. It defines the amount of time the bus master wants to retain PCI
bus ownership when it initiates a transaction. The default value of this register for the 82559ER is
08h. This can be converted to an actual time using the PCI specification (8* 1/PCIclk), to a value of
242ns.
Maximum Latency Register
The Maximum Latency (Max_Lat) register is an optional read only register for bus masters and is
not applicable to non-master devices. This register defines how often a device needs to access the
PCI bus. The default value of this register for the 82559ER is 18h. This can be converted to an
actual time using the PCI specification (18h* 1/PCIclk), to a value of 1 s.
Capability ID Register
The Capability ID is a byte register. It signifies whether the current item in the linked list is the
register defined for PCI Power Management. PCI Power Management has been assigned the value
of 01H.
Next Item Pointer
The Next Item Pointer is a byte register. It describes the location of the next item in the 82559ER’s
capability list. Since power management is the last item in the list, this register is set to 0b.
Power Management Capabilities Register
The Power Management Capabilities register is a word read only register. It provides information
on the capabilities of the 82559ER related to power management. The 82559ER reports a value of
FE21h if it is connected to an auxiliary power source and 7E21h otherwise. It indicates that the
82559ER supports wake-up in the D3 state if power is supplied, either V
31:27
26
25
Bits
00011b
(no V
11111b
(V
1b
1b
Default
AUX
AUX
)
)
Read Only
Read Only
Read Only
Read/Write
Table 8. Power Management Capability Register
PME Support. This five bit field indicates the power states in which
the 82559ER may assert PME#. The 82559ER supports wake-up in
all power states if it is fed by an auxiliary power supply (V
D0, D1, D2, and D3
D2 Support. If this bit is set, the 82559ER supports the D2 power
state.
D1 Support. If this bit is set, the 82559ER supports the D1 power
state.
hot
if it is fed by PCI power.
Description
cc
or V
AUX
.
AUX
Datasheet
) and