GD82559ER 824184 Intel, GD82559ER 824184 Datasheet - Page 33

• Manufacturer Part Number: GD82559ER 824184
• Manufacturer: Intel

Specifications of GD82559ER 824184

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

4.2.5
4.2.5.1
Datasheet
Note: The wake-up event is supported only if the PME Enable bit in the Power Management Control/
The internal initialization signal resets the PCI Configuration Space, MAC configuration, and
memory structure.
The behavior of the PCI RST# signal and the internal 82559ER initialization signal are shown in
the figure below.
Wake-up Events
There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two
events are detailed below.
Status (PMCSR) register is set. (The PMCSR is described in
Control/Status Register (PMCSR)” on page
“Interesting” Packet Events
In the power-down state, the 82559ER is capable of recognizing “interesting” packets. The
82559ER supports pre-defined and programmable packets that can be defined as any of the
following:
This allows the 82559ER to handle various packet types. In general, the 82559ER supports
programmable filtering of any packet in the first 128 bytes.
•
•
•
•
•
•
ISOLATE# trailing edge
ARP Packets (with Multiple IP addresses)
Direct Packets (with or without type qualification)
Neighbor Discovery Multicast Address Packet (‘ARP’ in IPv6 environment)
NetBIOS over TCP/IP (NBT) Query Packet (under IPv4)
Internetwork Package Exchange* (IPX) Diagnostic Packet
PCI RST#
Internal hardware
reset
PCI RST#
Internal hardware
reset
ISOLATE#
Internal hardware
reset
Figure 10. 82559ER Initialization upon PCI RST# and ISOLATE#
55.)
D0 - D2 power state
Internal reset
due to ISOLATE#
D3 power state
Networking Silicon — GD82559ER
Section 7.1.19, “Power Management
640 ns
640 ns
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