GD82559ER 824184 Intel, GD82559ER 824184 Datasheet - Page 85

• Manufacturer Part Number: GD82559ER 824184
• Manufacturer: Intel

Specifications of GD82559ER 824184

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

10.4.2.2
10.4.2.3
Datasheet
NOTE: Input test is done with 0.1V
PCI Timings
NOTES:
Flash Interface Timings
The 82559ER is designed to support up to 150 nanoseconds of Flash access time. The V
the Flash implementation should be connected permanently to 12 V. Thus, writing to the Flash is
controlled only by the FLWE# pin.
Table 26
illustrated in
1. Timing measurement conditions are illustrated in
2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section
3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times
4. Timing measurement conditions are illustrated in
5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal.
6. All PCI interface output drivers are floated when RST# is active.
4.2.3.2.
and input setup times than bussed signals. All other signals are bussed.
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
for testing input timing.
provides the timing parameters for the Flash interface signals. The timing parameters are
t
t
t
t
t
t
t
t
T
T
Symbol
val
val(ptp)
on
off
su
su(ptp)
h
rst
rst-clk
rst-off
Figure
29.
PCI CLK to Signal Valid Delay
PCI CLK to Signal Valid Delay (point-
to-point)
Float to Active Delay
Active to Float Delay
Input Setup Time to CLK
PCI Input Setup Time to CLK (point-to-
point)
Input Hold Time from CLK
Reset Active Time After Power Stable
PCI Reset Active Time After CLK
Stable
Reset Active to Output Float Delay
V
V
Input Signal Edge
step
step
(falling edge)
(rising edge)
V
Rate
max
CC
Parameter
overdrive. V
Table 24. Measure and Test Condition Parameters
Table 25. PCI Timing Parameters
max
0.285V
0.615V
0.4V
Figure
Figure
specifies the maximum peak-to-peak waveform allowed
1
CC
CC
CC
27.
28.
Networking Silicon — GD82559ER
Min
100
10
2
2
7
0
1
2
0.325V
0.475V
0.475V
0.325V
0.4V
1
Max
CC
11
12
28
40
CC
CC
CC
CC
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
V/ns
s
V
V
V
V
V
Max Delay
Max Delay
Min Delay
Min Delay
Notes
1, 2, 4
1, 2, 4
4, 5
4, 5
6, 7
6
1
1
6
6
PP
signal in
79