GD82559ER 824184 Intel, GD82559ER 824184 Datasheet - Page 67

• Manufacturer Part Number: GD82559ER 824184
• Manufacturer: Intel

Specifications of GD82559ER 824184

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

8.1.12
8.1.13
Datasheet
Note: The PMDR is initialized at ALTRST# reset only.
General Control Register
The General Control register is a byte register and is described below.
General Status Register
The General Status register is a byte register which indicates the link status of the 82559ER.
29
28:26
25
24
7:2
1
0
7:3
2
1
0
Bits
Bits
Bits
0b
000b
0b
0b
000000b
0b
0b
00000b
--
--
0b
Default
Default
Default
Read/Clear
Read Only
Read/Clear
Read/Clear
Read Only
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Table 11. Power Management Driver Register
Interesting Packet. This bit is set when an “interesting” packet is
received. Interesting packets are defined by the 82559ER packet
filters. This bit is cleared by writing 1b to it.
Reserved. These bits are reserved and should be set to 000b.
Reserved. These bit is reserved and should be set to 0b.
PME Status. This bit is a reflection of the PME Status bit in the Power
Management Control/Status Register (PMCSR). It is set upon a wake-
up event and is independent of the PME Enable bit.
This bit is cleared by writing 1b to it. This also clears the PME Status
bit in the PMCSR and de-asserts the PME signal. I
Reserved. These bits are reserved and should be set to 000000b.
Deep Power-Down on Link Down Enable. If a 1b is written to this
field, the 82559ER may enter a deep power-down state (sub-3 mA) in
the D2 and D3 power states while the link is down.
In this state, the 82559ER does not keep link integrity. This state is not
supported for point-to-point connection of two end stations.
Clockrun Signal Disable. If this bit is set to 1b, then the 82559ER will
always request the PCI clock signal. This mode can be used to
overcome potential receive overruns caused by Clockrun signal
latencies over 5 s.
Reserved. These bits are reserved and should be set to 00000b.
Duplex Mode. This bit indicates the wire duplex mode: full duplex (1b)
or half duplex (0b).
Speed. This bit indicates the wire speed: 100 Mbps (1b) or 10 Mbps
(0b).
Link Status Indication. This bit indicates the status of the link: valid
(1b) or invalid (0b).
Table 12. General Control Register
Table 13. General Status Register
Networking Silicon — GD82559ER
Description
Description
Description
61