FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 14

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

LXT1000 — Gigabit Ethernet Transceiver
14
B11
C10
B9
E10
C8
E8
D7
E6
C12
E13
B15
E15
E16
C20, E20,
D21, G22,
F23, H23,
J22, J24,
E18, C18
D17
B17
B11, C10,
B9, E10,
C8, E8, D7,
E6, C12,
E13
B15, E15
E16
1. I/O Column Coding: I = Input, O = Output
2. Complies with IEEE 802.3, Clauses 35.(GMII) and 22 (MII); Modes 1000 (GMII), 100 (MII), 10 (MII or Serial), Auto-
3. Complies with IEEE 802.3, Clause 36. NOTE: This section is an alternate listing of previously described pins.
Ball #
negotiation.
Table 2.
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_ER
RX_CLK
COL
CRS
TXD<9:0>
TX_CLK
GTX_CLK
RXD<9:0>
RBC0, RBC1
COMDET
LXT1000 GMII Signal Descriptions (Continued)
Symbol
MAC Data Interface - TBI Configuration
O
O
O
O
O
O
I
O
I
O
O
O
Type
1
Receive Data Bus. The width of this synchronous output bus varies with speed/mode:
1000: All 8 bits are driven.
100 and 10 MII mode: RXD<3:0> are driven; RXD<7:4> are held Low.
10 Serial: RXD<0> is driven; RXD<7:1> are held Low.
Receive Data Valid. This synchronous output is asserted when valid data is driven on
RXD.
Receive Error. For 1000 operation, this output is asserted when error symbols or
carrier-extension symbols are received. For 100 operation, it is asserted when error
symbols are received. For 10 operation, it is not asserted. It is always synchronous to
RX_CLK.
Receive Clock. This output clock is used to synchronize the receive output signals. Its
frequency depends upon the link speed:
1000: 125 MHz
100: 25 MHz (35/65 duty cycle)
10 MII or Auto-negotiation: 2.5 MHz
10 Serial: 10 MHz
Collision. This asynchronous output is asserted when a collision is detected (applies
to half-duplex links only). In full-duplex mode, this output is forced Low.
Carrier Sense. This asynchronous output is asserted when data is detected at the
twisted-pair interface.
Transmit Data Bus. This input bus must be synchronized to GTX_CLK.
Transmit Clock. 25 MHz output. Not used; provided as a utility.
Gigabit Transmit Clock. 125 MHz input clock
Receive Data Bus. This output data bus is synchronized to RBC0/RBC1.
Receive Clocks. Two 62.5 MHz output clocks are provided at these outputs. RBC0 is
180 degrees (8 ns = 1/2 period delay) with respect to RBC1.
Comma Detect. Toggles when comma sequence is detected in the receive data
stream.
3
- 1000-Only Operation
Description
Document #: 249276
Rev. Date: 07/20/01
Revision #: 002
Datasheet