FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 52

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

LXT1000 — Gigabit Ethernet Transceiver
2.5.4.1
52
Figure 21. 1000BASE-T Frame Structure
Operation Details
Figure 21
detail of all 1000 Mbps supported operations.
2.5.4.1.1 Transmitting/Receiving (Normal)
To transmit, the MAC asserts TX_EN and immediately begins driving preamble octets on TX_D.
The LXT1000 asserts CRS back to the MAC, and drives two SSD symbols on the line. The SSD
symbols overwrite the first two octets transmitted by the MAC, which are normally preamble
octets “55”. After transmitting the SSD, the LXT1000 begins transparent scrambling/encoding of
the stream. After the last Frame Check Sequence octet, the MAC de-asserts TX_EN, and the
LXT1000 responds by driving two symbols of convolutional reset (csreset) and two ESD symbols
before driving idle symbols. The csreset symbols return the Viterbi encoder to a default state during
the inter-packet gap.
As a receiver, the LXT1000 asserts CRS and RX_DV in response to receiving an SSD, and
immediately begins driving RX_D. Preamble octets “55 55” are substituted for the SSD, after that
the LXT1000 transparently decodes the received stream. The LXT1000 de-asserts RX_DV and
CRS when it receives the first csreset.
MAC Layer
PHY Layer
•
•
Packet concatentation, which allows MACs in half-duplex applications to concatenate packet
up to a maximum length of 8 KB. Gaps between packets are filled using a special symbol
allowing the PHY to maintain ownership of the link.
Jumbo frames. For full-duplex operations, the LXT1000 allows jumbo frames up to 10 KB,
with up to +/- 200 ppm of frequency tolerance on any clock.
p
introduces the following sections and accompanying figures, which provide further
SSD
2 symbols
Preamble, 7 bytes
55..55..55..55
DA
Address,
6 bytes
4D-PAM5 Encoding
.....
DA SA
SFD
5D
Address,
6 bytes
Packet, 64 to 1518 bytes
.....
SA
Length
2 bytes
T/L T/L D0
yp
2 symbols
csreset
46 to 1500 bytes
Inter Packet Gap
.....
ESD
2 symbols
>96 bits
Dn
FCS
Sequence,
4 bytes
.....
FCS
Document #: 249276
Rev. Date: 07/20/01
Revision #: 002
Datasheet