FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 18

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

LXT1000 — Gigabit Ethernet Transceiver
18
C22
D19
L5
K3
AC23
AA24,
AB14
D9, D11,
D12, E12,
C14, B13
N23
U22
F4
J2
B19
D6
D4
L23
K23
1. I/O Column Coding: I = Input, O = Output, A = Analog, PU = Pull Up (Internal)
Ball #
Table 6.
QSTAT
QCLK
MDDIS
MDINT
XI
XO
RBIAS
GBIAS
RESET
PWRDWN
P/D
P/D
P/D
P/D
P/D
N/C1
N/C2
LXT1000 Miscellaneous Signal Descriptions
Symbol
O, PU
I
I
O
I
O
AI
AI
I
I
-
-
-
-
-
-
-
Type
1
Quick Chip Status. Link-state monitoring. See
Interface” on page
Quick Clock. Clock input used for QSTAT feature. Maximum frequency is
25 MHz. (There is no minimum.)
Management Disable. When MDDIS is High, read and write operations on
the MDIO are disabled and most hardware control balls have continuous
control over their respective functions (some balls are read only at reset or
power-up). When MDDIS is Low, the MDIO supports read and write
operations, and hardware control balls establish only the initial values of their
respective functions.
Management Data Interrupt. When bit 18.1 = 1, an Active Low output
indicates status change. Interrupt is cleared by reading Register 19.
Crystal Input and Output. A 25 MHz clock must be supplied at this input,
either by placing a 25 MHz crystal across XI and XO, or by driving a 25 MHz
signal directly into XI. Refer to Functional Description on
requirements.
Bias Control. A 10.7 k , 1% resistor must be tied from this ball to ground.
GMII Bias. Tie these balls together, and then to the anode of a 0.1 f
capacitor. Tie the cathode of the capacitor to ground.
Reset. This active Low input is OR’ed with the control register Reset bit
(0.15). The LXT1000 reset cycle is extended 258 s (nominal) after Reset is
de-asserted. The transmitter is held disabled until the transmit clock
frequency is within specification.
Power Down. When High, PWRDWN forces the LXT1000 into hardware
power down mode, de-activating all functions and interfaces. This ball is
OR’ed with the Power Down bit 0.11.
Pull-down. Tie Low.
Note: Tie independently to ground or through its own resistor.
Pull-down. Tie Low.
Pull-down. Tie Low.
Pull-down. Tie Low.
Pull-down. Tie Low.
No Connect. Let ball float; do not connect to anything.
No Connect. Let ball float; do not connect to anything.
No Connect (N/C)
Pull Down (P/D)
34.
Description
Section 2.3.8, “Quick Status
page 20
Document #: 249276
Rev. Date: 07/20/01
Revision #: 002
Datasheet
for detailed