FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 16

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

LXT1000 — Gigabit Ethernet Transceiver
16
Y22
L2
R23
AA22
B21
T22
M24
M22
U24
1. I/O Column Coding: LHR = Input, Latched on Low-to-High edge of RESET (ignored thereafter); I, MD = Input, Latched on
2. MAC Interface Operating modes: GMII (1000 Mbps), MII (10 or 100 Mbps), Serial (10 Mbps).
Low-to-High edge of RESET, used thereafter only if Manual Control mode (MDDIS = 1).
Table 4.
Ball #
DUPLEX/
TX_TCLKN
AN_RSTRT
SMART_SPD
PAUSE/
TX_TCLKP
MASTER
CROSS
ANISOL
SER10
TBI
CONFIGURATI
ON
LXT1000 Configuration Signal Descriptions (Continued)
Symbol
I, MD
O
I, MD
LHR
I, MD
O
I, MD
I, MD
LHR
LHR
LHR
Type
1
Duplex Mode. When 21.15 = 0 (default), this input controls the duplex state of
the link. Its exact function varies depending on the state of AN_EN. For TBI
configurations, this input should be tied High.
When AN_EN is High, this bit enables advertising of full-duplex capabilities. (Bits
9.9, 4.8, and 4.6 are set High if the corresponding SPEED is also High).
When AN_EN is Low, this bit directly forces duplex state through MII bit 0.8; Low
= half duplex; High = full duplex.
TX_TCLKN (Transmit Jitter Test Clock). The internal 125 MHz clock used to
transmit data is output as a differential signal on Y22 and AA22 when 21.15 = 1.
Restart Auto Negotiation. A positive edge on AN_RSTRT restarts the Auto-
negotiation process. This signal controls the MII Control Register bit 0.9.
AN_RSTRT is relevant only when AN_EN is High.
Smart Speed Select. When High, this input enables SmartSpeed control.
SMART_SPD drives bit 16.7 (see
Pause Configuration. When 21.15 = 0 (default), this input determines the
settings of Pause (4.10) and ASM_DIR (4.11) during auto-negotiation. If this input
is High, both bits are set High; if Low, both are disabled.
TX_TCLKP (Transmit Jitter Test Clock). The internal 125 MHz clock used to
transmit data is output as a differential signal on Y22 and AA22 when 21.15 = 1.
Master/Slave Configuration. This configuration sets Port Type bit 9.10, which
indicates the Gigabit Master/Slave configuration. The default configuration, bit
9.12, interprets this setting as the preferred, but not required, mode.
High = Master (multi-port) configuration (Transmitter driven from local clock
source).
Low = Slave (single-port) configuration. (Transmitter driven from recovered
clock).
Crossover Selection. Determines TPAP/N and TPBP/N operation during auto-
negotiation and 10/100 operation. Crossover Selection is not used during 1000
operation.
When High, TPAP/N is an input; TPBP/N is an output (Switch configuration).
When Low, TPAP/N is an output; TPBP/N is an input (NIC/DTE configuration).
When set to mid-level voltage or left open, the device automatically determines
correct operation. Changing the state of this input generates an internal reset,
resulting in a new auto-negotiation cycle.
Auto Negotiate Isolate. When ANISOL is High, the auto-negotiation isolate
feature is enabled (refer to
drives 16.2.
Serial Mode. Applies when the MAC interface is used in the GMII configuration.
Determines how 10 Mbps links are handled and setting of bit 16.3:
GMII Configuration:
High = Serial mode (1 bit x 10 MHz)
Low = MII mode (4 bits x 2.5 MHz).
TBI Configuration:
For TBI configuration, pull Low.
Ten-Bit Interface (TBI) Mode. Determines MAC interface configuration and
setting of bit 16.1.
High = TBI Configuration
Low = GMII configurations.
“Auto-Negotiate Isolation” on page
Description
“SmartSpeed” on page
2
43).
44). ANISOL
Document #: 249276
Rev. Date: 07/20/01
Revision #: 002
Datasheet