FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 70

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

LXT1000 — Gigabit Ethernet Transceiver
3.2
3.2.1
3.2.2
3.2.3
70
Single-port Device
Single-port Device
Manual Slave
Manual Slave
1. If both sides choose “Multi-port Device” or “Single-Port Device”, they exchange random numbers, and the side with the higher
number prevails.
Table 26. Master/Slave Preferences/Outcomes
LXT1000
Test Information
Forced Gig Operation
For test purposes, Gigabit links may be brought up in forced mode, bypassing auto-negotiation that
is normally required to bring up the link. To bring up a forced link:
Gigabit Transmit Test Clock
The PAUSE and DUPLEX inputs may be re-configured as output balls that drive a differential 125
MHz transmit test clock. This test clock is required by the 802.3 standard, and is used to verify that
the device meets jitter requirements. This test mode is enabled by setting bit 21.15 = 1. When used
in this mode, the two clock outputs should be terminated by 50 tied to VCC. Refer to the
LXT1000 Design and Layout Guide for more details.
Scrambler/Encoder Disable (100M)
For testing purposes, the 100 Megabit scrambler and encoder can be independently disabled.
Disabling the encoder causes the MII interface to operate as a 5-bit symbol mode interface, rather
than the normal 4-bit mode transmission. RXD4 and TXD4 accommodate MACs accepting 5-bit
symbols. In this “5B” mode, the MAC is responsible for generating all PHY layer encoding,
including SFD, EFD, and idle code.
To disable the encoder when a 100M link has been established, set bit 16.11 = 1. To disable the
100M scrambler, set bit 16.12 = 1. To return to normal 100M operation, set 16.11 = 0 and
16.12 = 0.
•
•
•
•
Disable auto-negotiation by tying the AN_EN input Low, or setting MII Register bit 0.12 = 0.
Force the speed to 1000 Mbps by setting the SPEED<2:0> balls to “100” or setting MII bits
0.13 and 0.8 = 0 and 0.6 = 1.
Set one side to “Master” by setting the MASTER input ball High, or setting MII bits 9.12 and
9.11 = 1.
Set the other side to “Slave” by setting the MASTER input ball Low, or setting MII bit
9.12 = 1 and 9.11 = 0.
Preferences
Single-port Device
Manual Slave
Any other setting
Manual Slave
Link Partner
Resolved by a random number.
Master
Slave
Deadlock - link doesn’t come up.
LXT1000
Outcome
Slave
Master
Link Partner
Document #: 249276
Rev. Date: 07/20/01
Revision #: 002
Datasheet