FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 37

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

2.3.10
2.3.10.1
2.3.10.2
2.3.10.3
Datasheet
Document #: 249276
Revision #: 002
Rev. Date: 07/20/01
EXTEST
IDCODE
SAMPLE
HIGHZ
CLAMP
BYPASS
Table 17. Boundary Scan Supported Instructions
Table 18. BSR Mode of Operation
Name
JTAG Boundary Scan Interface
The LXT1000 includes an IEEE JTAG1149.1 boundary scan test port for board level testing. All
digital I/O balls are accessible. The physical interface consists of five balls (TRST, TMS, TDI,
TDO, and TCK), and includes a state machine, data register array, and instruction register. Pull
each of these balls High except TRST, which is pulled Low.
State Machine
The TAP controller is a 16 state machine driven by the TCK and TMS balls. Upon reset by TRST
the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS and TDI are
High for a period of five TCK periods.
Instruction Register
After the state machine resets, the IDCODE instruction is always invoked. The decode logic
ensures correct data flow to the Data registers according to the current instruction (see
Boundary Scan Register
Each BSR cell has two stages. A flip-flop and a latch are used for the serial shift stage and the
parallel output stage. There are four modes of operation (see
FFE8
FFFEH
FFF8H
FFCFH
FFEFH
FFFFH
Mode
Code
1
2
3
4
Capture
Shift
Update
System Function
External Test
ID Code Inspection
Sample Boundary
Force Float
Control Boundary to 1/0
Bypass Scan
Operation
Description
Gigabit Ethernet Transceiver — LXT1000
Table
Test
Normal
Normal
Normal
Test
Normal
Mode
18).
BSR
ID REG
BSR
Bypass
Bypass
Bypass
Data Register
Table
17).
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