FLLXT1000BA.C4QE000 Intel, FLLXT1000BA.C4QE000 Datasheet - Page 7

• Manufacturer Part Number: FLLXT1000BA.C4QE000
• Manufacturer: Intel

Specifications of FLLXT1000BA.C4QE000

• Lead Free Status / RoHS Status: Not Compliant

Tables
Datasheet
Document #: 249276
Revision #: 002
Rev. Date: 07/20/01
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NIC Application - Twisted-Pair Interface .............................................................74
1000BASE-T GMII Transmit Timing....................................................................78
1000BASE-T GMII Receive Timing.....................................................................79
100BASE-TX Transmit Timing ............................................................................80
100BASE-TX Receive Timing .............................................................................81
10BASE-T MII Transmit Timing...........................................................................82
10BASE-T Receive Timing..................................................................................83
10BASE-T SQE (Heartbeat) Timing....................................................................83
10BASE-T Jab and Unjab Timing .......................................................................84
10BASE-T Serial Transmit Timing ......................................................................85
10BASE-T Serial Start-of-Frame Timing .............................................................85
10BASE-T Serial End-of-Frame Timing ..............................................................86
Fast Link Pulse Timing ........................................................................................87
FLP Burst Timing.................................................................................................87
MDIO Write Timing..............................................................................................88
MDIO Read Timing..............................................................................................88
QSTAT Write Timing ...........................................................................................89
PHY Identifier Bit Mapping ..................................................................................93
Preliminary PBGA Package Specification .........................................................105
Ordering Information - Sample ..........................................................................106
Signal Type Abbreviations...................................................................................13
LXT1000 GMII Signal Descriptions .....................................................................13
LXT1000 Twisted-Pair Interface Signal Descriptions ..........................................15
LXT1000 Configuration Signal Descriptions........................................................15
LXT1000 LED Indicator Configuration Signal Descriptions.................................17
LXT1000 Miscellaneous Signal Descriptions ......................................................18
LXT1000 Power Supply Signal Descriptions.......................................................19
LXT1000 Boundary Scan Signal Descriptions ....................................................19
Mapping of Twisted-Pair Outputs to RJ-45s........................................................24
Crossover Control and Automatic Detection .......................................................25
MAC Interface Modes of Operation.....................................................................25
MAC Interface Transmit Signal Mapping.............................................................26
MAC Interface Receive Signal Mapping..............................................................26
Test Loopback Operation ....................................................................................28
Configuring the LXT1000 via Hardware Control Interface...................................34
LED Status Indication / PHY Addressing ............................................................36
Boundary Scan Supported Instructions...............................................................37
BSR Mode of Operation ......................................................................................37
JTAG ID Register ................................................................................................38
Initialization Modes..............................................................................................39
Determining Duplex State via Parallel Detection.................................................42
Transmission Pattern If Link Is Down..................................................................43
Pause and Asymmetric Pause Settings ..............................................................45
4B/5B Coding ......................................................................................................60
Configuring Master/Slave Relationship ...............................................................69
Master/Slave Preferences/Outcomes..................................................................69
Magnetics Requirements.....................................................................................71
Contents
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