PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 112

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 9-8:
DS61168D-page 112
Legend:
R = Readable bit
-n = Value at POR
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
Range
31:24
23:16
15:8
Bit
7:0
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
CHSIRQ<7:0>: Channel Transfer Start IRQ bits
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
Unimplemented: Read as ‘0’
See
31/23/15/7
CFORCE
R/W-1
R/W-1
Bit
U-0
Table 7-1: “Interrupt IRQ, Vector and Bit Location”
S-0
—
DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER
30/22/14/6
CABORT
R/W-1
R/W-1
Bit
U-0
S-0
—
S = Settable bit
W = Writable bit
‘1’ = Bit is set
29/21/13/5
PATEN
R/W-1
R/W-1
R/W-0
Bit
U-0
—
Preliminary
28/20/12/4
SIRQEN
CHAIRQ<7:0>
CHSIRQ<7:0>
R/W-1
R/W-1
R/W-0
Bit
U-0
—
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
AIRQEN
R/W-1
R/W-1
R/W-0
Bit
U-0
(1)
(1)
—
for the list of available interrupt IRQ sources.
26/18/10/2
© 2011-2012 Microchip Technology Inc.
R/W-1
R/W-1
Bit
U-0
U-0
—
—
x = Bit is unknown
25/17/9/1
R/W-1
R/W-1
Bit
U-0
U-0
—
—
24/16/8/0
R/W-1
R/W-1
Bit
U-0
U-0
—
—