PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 194

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 20-1:
DS61168D-page 194
Legend:
R = Readable bit
-n = Value at POR
bit 31-26 Unimplemented: Read as ‘0’
bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value
bit 15
bit 14
bit 13
bit 12-8
bit 7
bit 6
bit 5-4
Note 1:
Range
31:24
23:16
15:8
7:0
Bit
2:
3:
4:
5:
6:
0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute
•
•
•
0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute
0000000000 = No adjustment
1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
•
•
•
1000000000 = Minimum negative adjustment, subtracts 512 clock pulses every one minute
ON: RTCC On bit
1 = RTCC module is enabled
0 = RTCC module is disabled
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit
1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode
0 = Continue normal operation in Idle mode
Unimplemented: Read as ‘0’
RTSECSEL: RTCC Seconds Clock Output Select bit
1 = RTCC Seconds Clock is selected for the RTCC pin
0 = RTCC Alarm Pulse is selected for the RTCC pin
RTCCLKON: RTCC Clock Enable Status bit
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
Unimplemented: Read as ‘0’
RTSECSEL
This register is reset only on a Power-on Reset (POR).
The ON bit is only writable when RTCWREN = 1.
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
31/23/15/7
ON
R/W-0
R/W-0
R/W-0
Bit
U-0
—
(2,3)
RTCCON: RTC CONTROL REGISTER
(4)
RTCCLKON
30/22/14/6
(2,3)
R/W-0
Bit
U-0
U-0
R-0
—
—
29/21/13/5
W = Writable bit
‘1’ = Bit is set
SIDL
R/W-0
R/W-0
Bit
U-0
U-0
—
—
Preliminary
28/20/12/4
R/W-0
Bit
U-0
U-0
U-0
—
—
—
CAL<7:0>
(4)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RTCWREN
(1)
27/19/11/3
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(5)
26/18/10/2
RTCSYNC HALFSEC
© 2011-2012 Microchip Technology Inc.
R/W-0
Bit
U-0
U-0
R-0
—
—
x = Bit is unknown
25/17/9/1
R/W-0
R/W-0
Bit
U-0
R-0
—
CAL<9:8>
(6)
24/16/8/0
RTCOE
R/W-0
R/W-0
R/W-0
Bit
U-0
—