PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 33

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

3.0
The the MIPS32
the PIC32MX1XX/2XX family processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
3.1
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32
FIGURE 3-1:
© 2011-2012 Microchip Technology Inc.
- Multiply-accumulate and multiply-subtract
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
Note 1: This data sheet summarizes the features
instructions
2: Some registers and associated bits
CPU
Features
®
CPU
Enhanced Architecture (Release 2)
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS61113)
Reference Manual”, which is available
from
(www.microchip.com/PIC32). Resources
for the MIPS32
are available at http://www.mips.com.
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
®
M4K
the
MIPS32
®
Processor Core is the heart of
(RF/ALU/Shift)
Coprocessor
in
Execution
®
System
Core
Microchip
MDU
M4K
the
®
M4K
®
“PIC32
Processor Core
®
PROCESSOR CORE BLOCK DIAGRAM
web site
Family
FMT
Preliminary
in
• MIPS16e
• Simple Fixed Mapping Translation (FMT)
• Simple dual bus interface
• Autonomous multiply/divide unit
• Power control
• EJTAG debug and instruction trace
Bus Interface
Management
- Programmable exception vector base
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
- Bit field manipulation instructions
- 16-bit encoding of 32-bit instructions to
- Special PC-relative instructions for efficient
- SAVE and RESTORE macro instructions for
- Improved support for handling 8 and 16-bit
mechanism
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
- Maximum issue rate of one 32x16 multiply
- Maximum issue rate of one 32x32 multiply
- Early-in iterative divide. Minimum 11 and
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
- Extensive use of local gated clocks
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints
for interrupt handlers
improve code density
loading of addresses and constants
setting up and tearing down stack frames
within subroutines
data types
interrupt latency
per clock
every other clock
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
instruction)
Power
EJTAG
TAP
®
PIC32MX1XX/2XX
code compression
Dual Bus I/F
Debug I/F
Off-Chip
DS61168D-page 33