PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 177

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

REGISTER 17-2:
© 2011-2012 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14
bit 13-11 Unimplemented: Read as ‘0’
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
Range
31:24
23:16
15:8
Bit
7:0
ACKSTAT: Acknowledge Status bit
(when operating as I
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D_A: Data/Address bit (when operating as I
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
31/23/15/7
ACKSTAT
R/C-0, HS
R-0, HSC
IWCOL
Bit
U-0
U-0
—
—
I2C
30/22/14/6
X
TRSTAT
R/C-0, HS
STAT: I
R-0, HSC
I2COV
Bit
U-0
U-0
—
—
2
C™ master, applicable to master transmit operation)
2
C™ STATUS REGISTER
HS = Set in hardware
W = Writable bit
‘1’ = Bit is set
29/21/13/5
R-0, HSC
D_A
Bit
U-0
U-0
U-0
—
—
—
Preliminary
28/20/12/4
R/C-0, HSC
2
C slave)
Bit
U-0
U-0
U-0
—
—
—
P
2
C master, applicable to master transmit operation)
HSC = Hardware set/cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
R/C-0, HSC
Bit
U-0
U-0
U-0
—
—
—
S
PIC32MX1XX/2XX
2
C module is busy
26/18/10/2
R/C-0, HS
R-0, HSC
R_W
BCL
Bit
U-0
U-0
—
—
C = Clearable bit
25/17/9/1
GCSTAT
R-0, HSC
R-0, HSC
RBF
Bit
U-0
U-0
—
—
DS61168D-page 177
24/16/8/0
R-0, HSC
ADD10
R-0, HSC
TBF
Bit
U-0
U-0
—
—