PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 37

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

4.0
PIC32MX1XX/2XX microcontrollers provide 4 GB of
unified virtual memory address space. All memory
regions, including program, data memory, SFRs and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX1XX/2XX
devices to execute from data memory.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
• Simple memory mapping with Fixed Mapping
• Cacheable (KSEG0) and non-cacheable (KSEG1)
© 2011-2012 Microchip Technology Inc.
Note:
(KSEG0/KSEG1) mode address space
program space
runaway code
Translation (FMT) unit
address regions
MEMORY ORGANIZATION
This data sheet summarizes the features
of
devices. It is not intended to be a
comprehensive
detailed information, refer to Section 3.
“Memory Organization” (DS61115) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
the
PIC32MX1XX/2XX
reference
source.For
family
Preliminary
of
4.1
PIC32MX1XX/2XX microcontrollers implement two
address schemes: virtual and physical. All hardware
resources, such as program memory, data memory
and peripherals, are located at their respective physical
addresses. Virtual addresses are exclusively used by
the CPU to fetch and execute instructions as well as
access peripherals. Physical addresses are used by
bus master peripherals, such as DMA and the Flash
controller, that access memory independently of the
CPU.
The memory maps for the PIC32MX1XX/2XX devices
are illustrated in
PIC32MX1XX/2XX Memory Layout
PIC32MX1XX/2XX
Figure 4-1
and
Figure
DS61168D-page 37
4-2.