PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 170

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 16-3:
DS61168D-page 170
Legend:
R = Readable bit
-n = Value at POR
bit 31-29 Unimplemented: Read as ‘0’
bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 15-13 Unimplemented: Read as ‘0’
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4
Range
31:24
23:16
15:8
7:0
Bit
FRMERR: SPI Frame Error status bit
1 = Frame error detected
0 = No Frame error detected
This bit is only valid when FRMEN = 1.
SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
Unimplemented: Read as ‘0’
SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous data in
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR
Unimplemented: Read as ‘0’
31/23/15/7
SRMT
the SPIxBUF register.
Bit
U-0
U-0
U-0
R-0
—
—
—
SPIxSTAT: SPI STATUS REGISTER
30/22/14/6
SPIROV
R/W-0
Bit
U-0
U-0
U-0
—
—
—
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
29/21/13/5
SPIRBE
Bit
U-0
U-0
U-0
R-0
—
—
—
≠
SWPTR)
Preliminary
28/20/12/4
FRMERR
R/C-0, HS
Bit
R-0
R-0
U-0
—
HS = Set in hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
SPIBUSY
SPITBE
Bit
R-0
R-0
R-0
R-1
RXBUFELM<4:0>
TXBUFELM<4:0>
26/18/10/2
© 2011-2012 Microchip Technology Inc.
Bit
R-0
R-0
U-0
U-0
—
—
x = Bit is unknown
25/17/9/1
SPITBF
Bit
R-0
R-0
U-0
R-0
—
24/16/8/0
SPITUR
SPIRBF
Bit
R-0
R-0
R-0
R-0