S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 16

• Manufacturer Part Number: S25FL032P0XMFI011
• Description: IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

Specifications of S25FL032P0XMFI011

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom/Top
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 38mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

7.7
7.8
16
Status Register
Configuration Register
The Status Register contains the status and control bits that can be read or set by specific commands (see
Table 9.1 on page
operation of the device. (for details see
The Configuration Register contains the control bits that can be read or set by specific commands. These bits
configure different configurations and security features of the device.
Note: It is suggested that the Block Protection and Parameter sectors not be set to the same area of the
array; otherwise, the user cannot utilize the Parameter sectors if they are protected. The following matrix
shows the recommended settings.
Write In Progress (WIP): Indicates whether the device is performing a Write Registers, program or erase
operation.
Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.
Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected
against program and erase commands.
Erase Error (E_ERR): The Erase Error Bit is used as an Erase operation success and failure check.
Program Error (P_ERR): The Program Error Bit is used as an program operation success and failure check.
Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit
is set to 1 and the W#/ACC input is driven low. In this mode, the non-volatile bits of the Status Register
(SRWD, BP2, BP1, BP0) become read-only bits.
The FREEZE bit locks the BP2-0 bits in Status Register and the TBPROT and TBPARM bits in the
Configuration Register. Note that once the FREEZE bit has been set to ‘1’, then it cannot be cleared to ‘0’
until a power-on-reset is executed. As long as the FREEZE bit is set to ‘0’, then the other bits of the
Configuration Register, including FREEZE bit, can be written to.
The QUAD bit is non-volatile and sets the pin out of the device to Quad mode; that is, W#/ACC becomes
IO2 and HOLD# becomes IO3. The instructions for Serial, Dual Output, and Dual I/O reads function as
normal. The W#/ACC and HOLD# functionality does not work when the device is set in Quad mode.
The TBPARM bit defines the logical location of the 4 KB parameter sectors. The parameter sectors consist
of thirty two 4 KB sectors. All sectors other than the parameter sectors are defined to be 64-KB uniform in
size. When TBPARM is set to a ‘1’, the 4 KB parameter sectors starts at the top of the array. When
TBPARM is set to a ‘0’, the 4 KB parameter sectors starts at the bottom of the array. Note that once this bit
is set to a '1', it cannot be changed back to '0'.
The BPNV bit defines whether or not the BP2-0 bits in the Status Register are volatile or non-volatile.
When BPNV is set to a ‘1’, the BP2-0 bits in the Status Register are volatile and will be reset to binary 111
after power on reset. When BPNV is set to a ‘0’, the BP2-0 bits in the Status Register are non-volatile. Note
that once this bit is set to a '1', it cannot be changed back to '0'.
The TBPROT bit defines the operation of the block protection bits BP2, BP1, and BP0 in the Status
Register. When TBPROT is set to a ‘0’, then the block protection is defined to start from the top of the array.
When TBPROT is set to a ‘1’, then the block protection is defined to start from the bottom of the array. Note
that once this bit is set to a '1', it cannot be changed back to '0'.
23). These bits configure different protection configurations and supply information of
TBPARM
0
0
1
1
Table 9.8, S25FL032P Status Register on page
S25FL032P
TBPROT
D a t a
0
1
0
1
Table 7.1 Suggested Cross Settings
S h e e t
Parameter Sectors – Bottom
BP Protection – Top
(default)
Not recommended (Parameters & BP Protection are both Bottom)
Not recommended (parameters & BP Protection are both Top)
Parameter Sectors - Top of Array (high address)
BP Protection - Bottom of Array (low address)
S25FL032P_00_05 October 5, 2009
Array Overview
37):