S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 17

• Manufacturer Part Number: S25FL032P0XMFI011
• Description: IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

Specifications of S25FL032P0XMFI011

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom/Top
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 38mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

7.9
October 5, 2009 S25FL032P_00_05
Data Protection Modes
Note
(Default) indicates the value of each Configuration Register bit set upon initial factory shipment.
Spansion SPI Flash memory devices provide the following data protection methods:
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the
memory array that can be read but not programmed or erased.
and address ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM): The Write Protect (W#/ACC) input and the Status Register Write
Disable (SRWD) bit together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Register commands consist of
a clock pulse count that is a multiple of eight before executing them.
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Register (WRR)
– Parameter 4 KB Sector Erase (P4E)
– Parameter 8 KB Sector Erase (P8E)
– Quad Page Programming (QPP)
– OTP Byte Programming (OTPP)
Bit
7
6
5
4
3
2
1
0
Bit Name
TBPROT
TBPARM
FREEZE
QUAD
BPNV
NA
NA
NA
D a t a
-
-
Configures start of block protection
-
Configures BP2-0 bits in the Status Register
Configures Parameter sector location
Puts the device into Quad I/O mode
Locks BP2-0 bits in the Status Register
Table 7.2 Configuration Register Table
S h e e t
S25FL032P
Bit Function
Table 7.3
Not Used
Not Used
1 = Bottom Array (low address)
0 = Top Array (high address) (Default)
Do not use
1 = Volatile
0 = Non-volatile (Default)
1 = Top Array (high address)
0 = Bottom Array (low address) (Default)
1 = Quad I/O
0 = Dual or Serial I/O (Default)
1 = Enabled
0 = Disabled (Default)
and
Table 7.4
Description
shows the sizes
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