S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 41

• Manufacturer Part Number: S25FL032P0XMFI011
• Description: IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

Specifications of S25FL032P0XMFI011

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom/Top
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 38mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

9.14
October 5, 2009 S25FL032P_00_05
Page Program (PP)
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the currently selected page are programmed from the starting address of the same page
(from the address whose 8 least significant bits are all zero). CS# must be driven low for the entire duration of
the PP sequence. The command sequence is shown in
The device programs only the last 256 data bytes sent to the device. If the 8 least significant address bits (A7-
A0) are not all zero, all transmitted data that goes beyond the end of the currently selected page are
programmed from the starting address of the same page (from the address whose 8 least significant bits are
all zero). If fewer than 256 data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effect on the other bytes in the same page.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (BP2:BP0) (see
SCK
CS#
SCK
SI
CS#
SI
Mode 3
Mode 0
MSB
40
7
41
6
42
5
Data Byte 2
0
43
4
D a t a
1
Figure 9.17 Page Program (PP) Command Sequence
44
3
2
Command
2
45
3
1
46
Table 7.3 on page
4
S h e e t
0
47 48 49 50 51 52 53 54 55
5
7
MSB
S25FL032P
6
6
7
5
23 22 21
MSB
8
Data Byte 3
4
9
3
24 Bit Address
10
18).
2
Figure 9.17
1
3
28
0
2
29
1
30
MSB
and
0
7
31
MSB
7
6
32
Table 9.1 on page
6
5
Data Byte 256
33
5
4
34
Data Byte 1
PP
4
3
35 36 37 38 39
. The Status Register may
3
2
2
1
1
0
23.
0
41