S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 18

• Manufacturer Part Number: S25FL032P0XMFI011
• Description: IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

Specifications of S25FL032P0XMFI011

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom/Top
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 38mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

7.10
18
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Registers, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see
falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of
SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
Note: The HOLD Mode feature is disabled during Quad I/O Mode.
BP2
BP2
Status Register Block
Status Register Block
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BP1
BP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
BP0
Figure
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 7.4 TBPROT=1 (Starts Protection from BOTTOM of Array)
Table 7.3 TBPROT = 0 (Starts Protection from TOP of Array)
7.1.
3E0000h-3FFFFFh
3C0000h-3FFFFFh
3F0000h-3FFFFFh
380000h-3FFFFFh
300000h-3FFFFFh
200000h-3FFFFFh
000000h-3FFFFFh
000000h-00FFFFh
000000h-01FFFFh
000000h-03FFFFh
000000h-07FFFFh
000000h-0FFFFFh
000000h-1FFFFFh
000000h-3FFFFFh
Address Range
Address Range
Protected
Protected
None
None
S25FL032P
D a t a
(16) SA63:SA48
(32) SA63:SA32
(2) SA63:SA62
(4) SA63:SA60
(8) SA63:SA56
(64) SA63:SA0
(16) SA0:SA15
(32) SA0:SA31
(64) SA0:SA63
(2) SA0:SA1
(4) SA0:SA3
(8) SA0:SA7
Protected
Protected
(1) SA63
Sectors
Sectors
(1) SA0
0
0
Memory Array
Memory Array
S h e e t
000000h-3EFFFFh
000000h-3DFFFFh
000000h-3BFFFFh
000000h-3FFFFFh
000000h-37FFFFh
000000h-2FFFFFh
000000h-1FFFFFh
000000h-3FFFFFh
010000h-3FFFFFh
020000h-3FFFFFh
040000h-3FFFFFh
080000h-3FFFFFh
100000h-3FFFFFh
200000h-3FFFFFh
Address Range
Address Range
Unprotected
Unprotected
None
None
S25FL032P_00_05 October 5, 2009
Figure
7.1, standard use). If the
Unprotected
Unprotected
SA16:SA63
SA32:SA63
SA63:SA0
SA62:SA0
SA61:SA0
SA59:SA0
SA55:SA0
SA47:SA0
SA31:SA0
SA0:SA63
SA1:SA63
SA2:SA63
SA4:SA63
SA8:SA63
Sectors
Sectors
None
None
Total Memory
Total Memory
Portion of
Portion of
Protected
Protected
Area
Area
1/64
1/32
1/16
1/64
1/32
1/16
ALL
1/8
1/4
1/2
1/8
1/4
1/2
All
0
0