S25FL032P0XMFI011 Spansion Inc., S25FL032P0XMFI011 Datasheet - Page 40

• Manufacturer Part Number: S25FL032P0XMFI011
• Description: IC 32M CMOS 3V 104MHZ SPI BUS INTERFACE
• Manufacturer: Spansion Inc.

Specifications of S25FL032P0XMFI011

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Bottom/Top
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 38mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

40
Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 9.9
HPM either by setting the SRWD bit after driving W#/ACC low, or by driving W#/ACC low after setting the
SRWD bit. However, the device disables HPM only when W#/ACC is driven high.
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in
HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no
protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).
If W#/ACC is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the
Status Register) can be used.
The Status and Configuration registers originally default to 00h, when the device is first shipped from the
factory to the customer.
Note: HPM is disabled when the Quad I/O Mode is enabled (Quad bit = 1 in the Configuration Register).
W# becomes IO2; therefore, HPM cannot be utilized.
SCK
CS S #
SO
SI
ACC
W#/
1
1
0
0
SRWD
shows that neither W#/ACC or SRWD bit by themselves can enable HPM. The device can enter
Bit
1
0
0
1
Software
Protected
(SPM)
Hardware
Protected
(HPM)
0
Figure 9.16 Write Registers (WRR) Instruction Sequence – 16 data bits
Mode
1
2
High Impedance
I I nstruction
Status & Configuration Registers are Writable
(if WREN instruction has set the WEL bit). The
values in the SRWD, BP2, BP1, & BP0 bits &
those in the Configuration Register can be
changed
Status & Configuration Registers are Hardware
Write Protected. The values in the SRWD,
BP2, BP1, & BP0 bits & those in the
Configuration Register cannot be changed
3
4
Write Protection of Registers
5
6
S25FL032P
Table 9.9 Protection Modes
7
MSB
7
D a t a
8
6
9
5
Status Register In
10
S h e e t
4
11
3
12
2
13
1
Protected against Page
Program, Parameter
Sector Erase, Sector
Erase, and Bulk Erase
Protected against Page
Program, Sector Erase,
and Bulk Erase
14
0
15
Protected Area
MSB
7
16
S25FL032P_00_05 October 5, 2009
6
17
Configuration Register In
5
Table 7.3 on page
18
Memory Content
4
19
3
20
Ready to accept Page
Program, Parameter
Sector Erase, & Sector
Erase instructions
Ready to accept Page
Program, Sector Erase
instructions
2
21
Unprotected Area
1
22
18.
0
23