TDA9955HL/17/C1:55 NXP Semiconductors, TDA9955HL/17/C1:55 Datasheet - Page 29

• Manufacturer Part Number: TDA9955HL/17/C1:55
• Description: TDA9955HL/LQFP100/TRAYBDP//17/
• Manufacturer: NXP Semiconductors
• Type: Videor

Specifications of TDA9955HL/17/C1:55

• Resolution (bits): 8 b
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.75 V ~ 1.85 V, 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281545551; TDA9955HL/17/C1-S; TDA9955HL/17/C1-S

NXP Semiconductors
Table 33.
Legend: * = default value
[1]
TDA9955HL_1
Product data sheet
Addr Register
B9h
BAh
BBh
BCh
BDh
BEh
Fig 5.
In progressive case bits VS_F2_LINE_START[12:0] and VS_F2_LINE_WIDTH[7:0] must be set to logic 0.
VS_F1_PIX_S_LSB
VS_F1_PIX_MSB
VS_F1_PIX_E_LSB
VS_F2_PIX_S_LSB
VS_F2_PIX_MSB
VS_F2_PIX_E_LSB
pixel 1
HREF and VREF in interlaced case
HREF
line 1
Vertical sync registers (address B3h to BEh) bit description
(1)
blanking
HREF_START[11:0]
period
Bit
7 to 0 VS_F1_PIX_START[7:0]
7 to 4 VS_F1_PIX_START[11:8]
3 to 0 VS_F1_PIX_END[11:8]
7 to 0 VS_F1_PIX_END[7:0]
7 to 0 VS_F2_PIX_START[7:0]
7 to 4 VS_F2_PIX_START[11:8]
3 to 0 VS_F2_PIX_END[11:8]
7 to 0 VS_F2_PIX_END[7:0]
HIGH during active video;
LOW during horizontal blanking period
Symbol
active video
active video
field 1
field 2
Rev. 01 — 17 March 2008
Triple 8-bit analog-to-digital video converter for HDTV
Access Value
W
W
W
W
W
W
W
W
HREF_END[11:0]
…continued
VREF
01h*
0h*
0h*
01h*
01h*
0h*
0h*
01h*
VREF_F1_START[10:0]
VREF_F1_WIDTH[7:0]
LOW during active video;
HIGH during vertical blanking period
VREF_F2_START[10:0]
VREF_F2_WIDTH[7:0]
VREF changes state at pixel 1
VREF_F1_START[10:0]
VREF_F1_WIDTH[7:0]
Description
vertical sync pixel start for field
1: position in number of pixels of the
rising edge of the VS signal
generated by the timing generator
for field 1; if 0, VS stays LOW
vertical sync pixel end for field 1
(LSB): position in number of pixels
of the falling edge of the VS signal
generated by the timing generator
for field 1; if 0, VS stays LOW
vertical sync pixel start for field
2: position in number of pixels of the
rising edge of the VS signal
generated by the timing generator
for field 2
vertical sync pixel end for field 2:
position in number of pixels of the
falling edge of the VS signal
generated by the timing generator
for field 2
TDA9955HL
© NXP B.V. 2008. All rights reserved.
001aaa291
(1)
29 of 52