TDA9955HL/17/C1:55 NXP Semiconductors, TDA9955HL/17/C1:55 Datasheet - Page 52

• Manufacturer Part Number: TDA9955HL/17/C1:55
• Description: TDA9955HL/LQFP100/TRAYBDP//17/
• Manufacturer: NXP Semiconductors
• Type: Videor

Specifications of TDA9955HL/17/C1:55

• Resolution (bits): 8 b
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.75 V ~ 1.85 V, 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935281545551; TDA9955HL/17/C1-S; TDA9955HL/17/C1-S

NXP Semiconductors
18. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 7
I
2
C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 10
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Analog multiplexers. . . . . . . . . . . . . . . . . . . . . . 7
R/P
Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Automatic Gain Control (AGC) . . . . . . . . . . . . . 7
Sync slicing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Activity detection. . . . . . . . . . . . . . . . . . . . . . . . 8
Sync detection and selection . . . . . . . . . . . . . . 8
Sync Detection Recognition and Separation . . 8
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . 8
Sync multiplexers . . . . . . . . . . . . . . . . . . . . . . . 8
Color conversion . . . . . . . . . . . . . . . . . . . . . . . . 9
4 : 2 : 2 downsample filters . . . . . . . . . . . . . . . . 9
Range control . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 : 2 : 2 formatter . . . . . . . . . . . . . . . . . . . . . . . 9
Video port selection . . . . . . . . . . . . . . . . . . . . 10
Output buffers . . . . . . . . . . . . . . . . . . . . . . . . . 10
VHREF timing generator. . . . . . . . . . . . . . . . . 10
I
Power management . . . . . . . . . . . . . . . . . . . . 10
Sync timing measurement . . . . . . . . . . . . . . . 10
I
Registers definitions . . . . . . . . . . . . . . . . . . . . 11
Version register. . . . . . . . . . . . . . . . . . . . . . . . 17
Input selection register . . . . . . . . . . . . . . . . . . 17
Sync detection recognition and separation
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLL registers. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pixel clocks generation registers . . . . . . . . . . 19
Pixel clocks generation registers . . . . . . . . . . 21
Clamp levels registers. . . . . . . . . . . . . . . . . . . 22
Video gain registers (GAIN_RV, GAIN_BU,
GAIN_GY). . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Sync timing measurement registers . . . . . . . . 23
Color space conversion registers . . . . . . . . . . 24
2
2
C-bus serial interface . . . . . . . . . . . . . . . . . . 10
C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 10
R
, B/P
B
and G/Y channels. . . . . . . . . . . . . . 7
Triple 8-bit analog-to-digital video converter for HDTV
9.2.11
9.2.12
9.2.13
9.2.14
9.2.15
9.2.16
9.2.17
9.2.18
9.2.19
9.2.20
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 41
Thermal characteristics . . . . . . . . . . . . . . . . . 41
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 49
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision history . . . . . . . . . . . . . . . . . . . . . . . 50
Legal information . . . . . . . . . . . . . . . . . . . . . . 51
Contact information . . . . . . . . . . . . . . . . . . . . 51
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Line and pixel counters . . . . . . . . . . . . . . . . . 26
Prefiltering register (PRE_FILTERS) . . . . . . . 34
Range control registers . . . . . . . . . . . . . . . . . 34
Output formatter register . . . . . . . . . . . . . . . . 35
Sync output selection registers . . . . . . . . . . . 36
Output polarity control register . . . . . . . . . . . . 36
Video ports control register . . . . . . . . . . . . . . 37
Data enable signal control register. . . . . . . . . 37
Software reset registers . . . . . . . . . . . . . . . . . 38
Power-down control registers . . . . . . . . . . . . . 39
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 51
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51
TDA9955HL
Document identifier: TDA9955HL_1
Date of release: 17 March 2008
All rights reserved.