DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 17

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

3 0 Functional Description
During transmission of a packet from the SONIC-T the
transceiver will always loop the packet back to the
SONIC-T The SONIC-T will use this to monitor the packet
as it is being transmitted The CRC and source address of
the looped back packet are checked with the CRC and
source address that were transmitted If they do not match
an error bit is set in the status of the transmitted packet (see
Packet Monitored Bad PMB in the Transmit Control Regis-
ter Section 6 3 4) Data is not written to the receive FIFO
during this monitoring process unless a Loopback mode has
been selected (see Section 3 7)
Receive Logic The receive logic contains the command
control and status registers that govern the operations of
the receive section It generates the control signals for writ-
ing data to the receive FIFO processes error signals ob-
tained from the CRC checker and the deserializer activates
the ‘‘packet reject’’ signal to the RSM for rejecting packets
and posts the applicable status in the Receive Control regis-
ter
Deserializer This section deserializes the serial input data
stream and provides a byte clock for the address compara-
tor and receive logic It also synchronizes the CRC checker
to begin operation (after SFD is detected) and checks for
proper frame alignment with respect to CRS going inactive
at the end of reception
Address Comparator The address comparator latches the
Destination Address (during reception or loopback) or
Source Address (during transmission) and determines
whether the address matches one of the entries in the CAM
CRC Checker The CRC checker calculates the 4-byte
Frame Check Sequence (FCS) field from the incoming data
stream and compares it with the last 4-bytes of the received
packet The CRC checker is active for both normal recep-
tion and self-reception during transmission
Content Addressable Memory (CAM) The CAM contains
16 user programmable entries and 1 pre-programmed
Broadcast address entry for complete filtering of received
packets The CAM can be loaded with any combination of
Physical and Multicast Addresses (see Section 4 2) See
Section 6 1 for the procedure on loading the CAM registers
3 3 2 MAC Transmit Section
The transmit section (Figure 3-7) is responsible for reading
data from the transmit FIFO and transmitting a serial data
(Continued)
FIGURE 3-7 MAC Transmitter
17
Binary Exponential Backoff Algorithm before reattempting
stream onto the network in conformance with the IEEE
802 3 Carrier Sense Multiple Access with Collision Detec-
tion (CSMA CD) standard The Transmit Section consists of
the following blocks
Transmit State Machine (TSM) The TSM controls the
functions of the serializer preamble generator and JAM
generator It determines the proper sequence of events that
the transmitter follows under various network conditions If
no collision occurs the transmitter prefixes a 62-bit pream-
ble and 2-bit Start of Frame Delimiter (SFD) at the beginning
of each packet and then sends the serialized data At the
end of the packet an optional 4-byte CRC pattern is ap-
pended If a collision occurs the transmitter switches from
transmitting data to sending a 4-byte Jam pattern to notify
all nodes that a collision has occurred Should the collision
occur during the preamble the transmitter waits for it to
complete before jamming After the transmission has com-
pleted the transmitter writes status in the Transmit Control
register (see Section 6 3 4)
Protocol State Machine The protocol state machine as-
sures that the SONIC-T obeys the CSMA CD protocol Be-
fore transmitting this state machine monitors the carrier
sense and collision signals for network activity If any other
nodes are currently transmitting the SONIC-T defers its
transmission until the network is quiet It then transmits after
its Interframe Gap Timer (9 6
frame Gap time is divided into two portions During the first
6 4
Gap timer Beyond this time however network activity is
ignored and the state machine waits the remaining 3 2
before transmitting If the SONIC-T experiences a collision
during a transmission it switches from transmitting data to
transmitting a 4-byte JAM pattern (4 bytes of all 1’s) before
ceasing to transmit The SONIC-T then waits a random
number of slot times (51 2 s) determined by the Truncated
another transmission In this algorithm the number of slot
times to delay before the nth retransmission is chosen to be
a random integer r in the range of
If a collision occurs on the 16th transmit attempt the
SONIC-T aborts transmitting the packet and reports an ‘‘Ex-
cessive Collisions’’ error in the Transmit Control register
s any new network activity will restart the Interframe
where k
0
s
e
r
s
min(n 10)
2
s) has expired The Inter-
k
TL F 11719 – 10
s