DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 59

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

Figure 7-5 illustrates the SONIC-T’s transitions through
7 0 Bus Interface
7 3 3 1 Bus Status Transitions
When the SONIC-T acquires the bus it only transfers data
to from a single area in memory (i e TDA TBA RDA RBA
RRA or CDA) Thus the bus status pins remain stable for
the duration of the block transfer cycle with the following
three exceptions 1) if the SONIC-T is accessed during a
block transfer S2–S0 indicates bus idle during the register
access then returns to the previous status 2) if the
SONIC-T finishes writing the Source Address during a block
transfer S2–S0 changes from 0 1 0 to 0 1 1 or 3) during
an RDA access between the RXpkt seq no and RXpkt link
access and between the RXpkt link and RXpkt in use ac-
cess S2 –S0 will respectively indicate idle 1 1 1 for 2 or 1
bus clocks Status will be valid on the falling edge of AS or
rising edge of ADS
memory during the process of transmission and reception
During transmission the SONIC-T reads the descriptor in-
formation from the TDA and then transmits data of the
packet from the TBA The SONIC-T moves back and forth
between the TDA and TBA until all fragments and packets
are transmitted During reception the SONIC-T takes one of
two paths In the first case (path A) when the SONIC-T
detects EOL
accepted packet into the RBA and then writes the descrip-
tor information to the RDA If the RBA becomes depleted
(i e RBWC0 1
resource descriptor In the second case (path B) when the
SONIC-T detects EOL
rereads the RXpkt link field to determine if the system has
e
k
0 from the previous reception it buffers the
EOBC) it moves to the RRA to read a
e
1 from the previous reception it
(Continued)
FIGURE 7-5 Bus Status Transitions
59
reset the EOL bit since the last reception If it has the
SONIC-T buffers the packet as in the first case Otherwise
it rejects the packet and returns to idle
7 3 4 Bus Mode Compatibility
For compatibility with different microprocessor and bus ar-
chitectures the SONIC-T operates in one of two modes (set
by the BMODE pin) called the National Intel or little endian
mode (BMODE tied low) and the Motorola or big endian
mode (BMODE tied high) The definitions for several pins
change depending on the mode the SONIC-T is in Table
7-2 shows these changes These modes affect both master
and slave bus operations with the SONIC-T
BR HOLD
BG HLDA
MRW MWR
SRW SWR
DSACK0 RDYi
DSACK1 RDYo
AS ADS
INT INT
Pin Name
TABLE 7-2 Bus Mode Compatibility
(National Intel)
BMODE
HOLD
HLDA
MWR
SWR
RDYi
RDYo
ADS
INT
e
0
BMODE
(Motorola)
BR
BG
MRW
SRW
DSACK0
DSACK1
AS
INT
TL F 11719 – 32
e
1