DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 40

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

12 11
6 0 SONIC-T Registers
6 3 2 Data Configuration Register
(RA
This register (Figure 6-5) establishes the bus cycle options for reading writing data to from 16- or 32-bit memory systems
During a hardware reset bits 15 and 13 are cleared all other bits are unaffected (Because of this the first thing the driver
software does to the SONIC-T should be to set up this register ) All bits are unaffected by a software reset This register must
only be accessed when the SONIC-T is in reset mode (i e the RST bit is set in the Command register)
Bit
15
14
13
r
k
EXBUS
e
5 0
r w
15
read only r w
l
EXBUS EXTENDED BUS MODE
Setting this bit enables the Extended Bus mode which enables the following
1 Extended Programmable Outputs EXUSR
2 Synchronous Termination STERM This changes the TXC pin from the External ENDEC interface into a
3 Asynchronous Bus Retry Causes BRT to be clocked in asynchronously off the falling edge of bus clock This only
Must be 0
LBR LATCHED BUS RETRY
The LBR bit controls the mode of operation of the BRT signal (see pin description Section 2 0) It allows the BUS
Retry operation to be latched or unlatched
0 Unlatched mode The assertion of BRT forces the SONIC-T to finish the current DMA operation and get off the bus
1 Latched mode The assertion of BRT forces the SONIC-T to finish the current DMA operation as above however
Note Unless LBR is set to a ‘‘1’’ BRT must remain asserted at least until the SONIC-T has gone idle See sec 7 3 6
PO1 PO0 PROGRAMMABLE OUTPUTS
The PO1 PO0 bits individually control the USR1 0 pins respectively when SONIC-T is a bus master (HLDA or BGACK
is active) When PO1 PO0 are set to a 1 the USR1 USR0 pins are high during bus master operations and when
these bits are set to a 0 the USR1 USR0 pins are low during bus master operations
e
external ENDEC interface into four programmable user outputs EXUSR
USR
these four pins will be TRI-STATE and will remain that way until the DCR is changed If EXBUS is enabled then
these pins will remain TRI-STATE until the SONIC-T becomes a bus master at which time they will be driven
according to the DCR2 If EXBUS is disabled then these four pins work normally as external ENDEC interface pins
synchronous memory termination input for compatibility with Motorola style processors This input is only useful
when Asynchronous Bus mode is selected (bit 10 below is set to ‘‘0’’) and the Bus Mode is set to Motorola Mode
(BMODE
EXBUS is enabled this pin will remain TRI-STATE until the SONIC-T becomes a bus master at which time it will
become the STERM input If EXBUS is disabled then this pin works normally as the TXC pin for the external ENDEC
interface
applies however when the SONIC-T is operating in asynchronous mode (bit 10 below is set to ‘‘0’’) If EXBUS is not
set XTO (BRT) is sampled synchronously off the rising edge of bus clock
The SONIC-T will retry the operation when BRT is deasserted
the SONIC-T will not retry until BRT is deasserted and the BR bit in the ISR (see Section 6 3 6) has been reset and
BRT is deasserted Hence the mode has been latched on until the BR bit is cleared
14
1h)
0
e
k
read write
1 0
LBR
r w
13
e
l
1) On hardware reset this pin will be TRI-STATE and will remain that way until the DCR is changed If
These outputs are programed with bits 15-12 in the DCR2 (see Section 6 3 7) On hardware reset
PO1
r w
12
PO0 SBUS USR1 USR0 WC1
r w
EXBUS
LBR
PO0 PO1
SBUS
USR0 USR1
WC0 WC1
DW
BMS
RFT0 RFT1
TFT0 TFT1
11
(Continued)
Field
FIGURE 6-5 Data Configuration Register
r w
10
r w
9
EXTENDED BUS MODE
LATCHED BUS RETRY
PROGRAMMABLE OUTPUTS
SYNCHRONOUS BUS MODE
USER DEFINABLE PINS
WAIT STATE CONTROL
DATA WIDTH SELECT
BLOCK MODE SELECT FOR DMA
RECEIVE FIFO THRESHOLD
TRANSMIT FIFO THRESHOLD
k
3 0
r w
8
l
40
Description
This changes the TXD LBK RXC and RXD pins from the
r w
7
Meaning
WC0
r w
6
DW
r w
5
k
3 0
BMS RFT1 RFT0 TFT1 TFT0
r w
4
l
respectively which are similar to
r w
3
r w
2
r w
1
r w
0