DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 95

no-image

DP83934CVUL20

Manufacturer Part Number
DP83934CVUL20
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of DP83934CVUL20

Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
160
Lead Free Status / RoHS Status
Not Compliant
9 0 AC and DC Specifications
REGISTER WRITE BMODE
Note 1 This figure shows a slave access to the SONIC-T when the SONIC-T is idle or rather not in master mode If the SONIC-T is a bus master there will be
some differences as noted in the Memory Arbitration Slave Access diagram The BSCK states (T1 T2 etc ) are the equivalent processor states during a slave
access
Note 2 bcyc
Number
T56
T60
T63
T64
T69
T69a
T70a
T71a
T75b
T77
T77a
T77b
T78
T79a
T81
T83
T84
T85a
e
bus clock cycle time (T3)
CS Asynchronous Setup to BSCK (Notes 3 4)
CS Valid to SMACK Low (Notes 2 3 4)
Register Address Setup to SAS
Register Address Hold from SAS
SAS Asynchronous Setup to BSCK (Notes 3 4)
SAS Asynchronous Setup to BSCK (Notes 3 5)
SRW (Write) Setup to SAS
SRW (Write) Hold from SAS
BSCK to DSACK0 1 Low
CS to DSACK0 1 High (Note 5)
SAS to DSACK0 1 High (Note 5)
BSCK to DSACK0 1 TRI-STATE (Note 5)
Skew between DSACK0 1
BSCK to SMACK High (Note 5)
BSCK to SMACK Low
Register Write Data Setup to BSCK
Register Write Data Hold from BSCK
Minimum CS Deassert Time (Notes 2 3)
e
1 (Note 1)
Parameter
(Continued)
95
Min
14
8
1
6
8
7
5
4
8
8
1
20 MHz
Max
22
20
31
19
19
22
5
3
Min
12
7
1
5
7
6
4
3
7
7
1
25 MHz
Max
20
18
29
17
17
20
5
3
TL F 11719 – 91
Units
bcyc
bcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Related parts for DP83934CVUL20