DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 87

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

9 0 AC and DC Specifications
BUS REQUEST TIMING BMODE
Note 1 A block transfer by the SONIC-T can be pre-empted from the bus by deasserting HLDA provided HLDA is asserted T46 before the rising edge of the last T2
in the current access
Note 2 The assertion edge for HOLD is dependent upon the PH bit in the DCR2 The default situation is shown wih a solid line in the timing diagram T43 and T44
apply for both modes Also if HLDA is asserted when the SONIC-T wants to acquire the bus HOLD will not be asserted until HLDA has been deasserted first
Note 3 S
Note 4 This timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns earlier enabling other devices to drive
these lines without contention
Number
T43
T44
T45
T46
T51
T52
T53
T55
T55b
k
2 0
l
will indicate IDLE at the end of T2 if the last operation is a read operation or at the end of Th if the last operation is a write operation
BSCK to HOLD High (Note 2)
BSCK to HOLD Low (Note 2)
HLDA Asynchronous Setup Time to BSCK
HLDA Synchronous Deassert Setup Time
(Note 1)
BSCK to Address ADS MWR DS ECS
USR
BSCK to Data TRI-STATE
BSCK to USR
BSCK to Bus Status Valid
S
k
2 0
k
1 0
l
Hold from BSCK
l
and EXUSR
k
1 0
e
l
Parameter
0
or EXUSR
k
3 0
l
TRI-STATE (Note 4)
k
(Continued)
3 0
l
Valid
87
Min
7
7
3
20 MHz
Max
18
19
37
39
34
29
Min
6
6
3
25 MHz
Max
16
17
35
37
32
27
TL F 11719 – 68
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns