DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 18

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

3 0 Functional Description
Serializer After data has been written into the 32-byte
transmit FIFO the serializer reads byte wide data from the
FIFO and sends a NRZ data stream to the Manchester en-
coder The rate at which data is transmitted is determined
by the transmit clock (TXC) The serialized data is transmit-
ted after the SFD
Preamble Generator The preamble generator prefixes a
62-bit alternating ‘‘1 0’’ pattern and a 2-bit ‘‘1 1’’ SFD pat-
tern at the beginning of each packet This allows receiving
nodes to synchronize to the incoming data The preamble is
always transmitted in its entirety even in the event of a colli-
sion This assures that the minimum collision fragment is 96
bits (64 bits of normal preamble and 4 bytes or 32 bits of
JAM pattern)
CRC Generator The CRC generator calculates the 4-byte
FCS field from the transmitted serial data stream If en-
abled the 4-byte FCS field is appended to the end of the
transmitted packet (see Section 4 6)
For bridging or switched ethernet applications the CRC
Generator can be inhibited by setting bit 13 in the Transmit
Control Register (Section 6 3 4) This feature is used when
an ethernet segment has already received a packet with a
CRC appended and needs to forward it another ethernet
segment
Jam Generator The Jam generator produces a 4-byte pat-
tern of all 1’s to assure that all nodes on the network sense
the collision When a collision occurs the SONIC-T stops
transmitting data and enables the Jam generator If a colli-
sion occurs during the preamble the SONIC-T finishes
transmitting the preamble before enabling the Jam genera-
tor (see Preamble Generator above)
3 4 DATA WIDTH AND BYTE ORDERING
The SONIC-T can be programmed to operate with either
32-bit or 16-bit wide memory The data width is configured
during initialization by programming the DW bit in the Data
Configuration Register (DCR) (see Section 6 3 2) If the
16-bit data path is selected data is driven on pins D15–D0
The SONIC-T also provides both Little Endian and Big Endi-
an byte-ordering capability for compatibility with National In-
tel or Motorola microprocessors respectively by selecting
the proper level on the Bus Mode (BMODE) pin
Little Endian (National Intel) Mode (BMODE
byte orientation for received and transmitted data in the Re-
ceive Buffer Area (RBA) and Transmit Buffer Area (TBA) of
system memory is as follows
15
31
Byte 1
Byte 3
MSB
MSB
16-Bit Word
24
8
7
23
Byte 0
Byte 2
LSB
32-Bit Long Word
16
0
15
Byte 1
8
(Continued)
7
e
Byte 0
LSB
0) The
0
18
Big Endian (Motorola) Mode (BMODE
entation for received and transmitted data in the RBA and
TBA is as follows
3 5 FIFO AND CONTROL LOGIC
The SONIC-T incorporates two independent 32-byte FIFOs
for transferring data to from the system interface and from
to the network The FIFOs providing temporary storage of
data free the host system from the real-time demands on
the network
The way in which the FIFOS are emptied and filled is con-
trolled by the FIFO threshold values and the Block Mode
Select bits (BMS) (see Section 6 3 2) The threshold values
determine how full or empty the FIFOs are allowed to be
before the SONIC-T will request access of the bus to get
more data from memory or buffer more data to memory
When Block Mode is enabled the number of bytes trans-
ferred is determined by the threshold value For example if
the threshold for the receive FIFO is 4 words then the SON-
IC-T will always transfer 4 words from the receive FIFO to
memory If Empty Fill mode is enabled however the num-
ber of bytes transferred is the number required to fill the
transmit FIFO or empty the receive FIFO The manner in
which the threshold affects reception and transmission of
packets is discussed below in Sections 3 5 1 and 3 5 2
3 5 1 Receive FIFO
To accommodate the different transfer rates the receive
FIFO (Figure 3-8) serves as a buffer between the 8-bit net-
work (deserializer) interface and the 16 32-bit system inter-
face The FIFO is arranged as a 4-byte wide by 8 deep
memory array (8-long words or 32 bytes) controlled by
three sections of logic During reception the Byte Ordering
logic directs the byte stream from the deserializer into the
FIFO using one of four write pointers Depending on the
selected byte-ordering mode data is written either least sig-
nificant byte first or most significant byte first to accommo-
date little or big endian byte-ordering formats respectively
As data enters the FIFO the Threshold Logic monitors the
number of bytes written in from the deserializer The pro-
grammable threshold (RFT1 0 in the Data Configuration
Register see Section 6 3 2) determines the number of
words (or long words) written into the FIFO from the MAC
unit before a direct memory access (DMA) request for sys-
tem memory occurs When the threshold is reached the
15
31
Byte 0
Byte 0
LSB
LSB
16-Bit Word
24
8
7
23
Byte 1
Byte 1
MSB
32-Bit Long Word
16
0
15
Byte 2
e
8
1) The byte ori-
7
Byte 3
MSB
0