DP83934CVUL20 National Semiconductor, DP83934CVUL20 Datasheet - Page 8

• Manufacturer Part Number: DP83934CVUL20
• Manufacturer: National Semiconductor

Specifications of DP83934CVUL20

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

NETWORK INTERFACE PINS (Continued)
BUS INTERFACE PINS (BOTH BUS MODES)
OSCIN
OSCOUT
BMODE
D31–D0
A31 –A1
RA5 –RA0
RESET
S2 –S0
BSCK
CS
Symbol
2 0 Pin Description
Driver
Type
TRI
TRI
TP
TP
Direction
I O Z
O Z
O
O
I
I
I
I
I
I
(Continued)
CRYSTAL FEEDBACK INPUT OR EXTERNAL OSCILLATOR INPUT This signal is used to
provide clocking signals for the internal ENDEC A crystal may be connected to this pin along
with OSCOUT or an oscillator module may be used See Section 8 1 3 for more information
about using an oscillator or crystal
CRYSTAL FEEDBACK OUTPUT This signal is used to provide clocking signals for the internal
ENDEC A crystal can be connected to this pin along with OSCIN See Section 8 1 3 for more
information about using an oscillator or crystal
BUS MODE This input enables the SONIC-T to be compatible with standard microprocessor
buses The level of this pin affects byte ordering (little or big endian) and controls the operation
of the bus interface control signals A high level (tied to V
endian) and a low level (tied to ground) selects National Intel mode (little endian) Note the
alternate pin definitions for AS ADS MRW MWR INT INT BR HOLD BG HLDA SRW SWR
DSACK0 RDYo and DSACK1 RDYi (See Sections 7 3 1 7 3 4 and 7 3 5 for bus interface
information )
DATA BUS These bidirectional lines are used to transfer data on the system bus When the
SONIC-T is a bus master 16-bit data is transferred on D15– D0 and 32-bit data is transferred on
D31–D0 When the SONIC-T is accessed as a slave register data is driven onto line D15– D0
D31–D16 are held TRI-STATE
ADDRESS BUS These signals are used by the SONIC-T to drive the DMA address after the
SONIC-T has acquired the bus Since the SONIC-T aligns data to word boundaries only 31
address lines are needed
REGISTER ADDRESS BUS These signals are used to access SONIC-T’s internal registers
When the SONIC-T is accessed the CPU drives these lines to select the desired SONIC-T
register
RESET This signal is used to hardware reset the SONIC-T When asserted low the SONIC-T
transitions into the reset state after 10 transmit clocks or 10 bus clocks if the bus clock period is
greater than the transmit clock period
BUS STATUS These three signals provide a continuous status of the current SONIC-T bus
operations See Section 7 3 3 for status definitions
BUS CLOCK This clock provides the timing for the SONIC-T DMA engine
CHIP SELECT The system asserts this pin low to access the SONIC-T’s registers The
registers are selected by placing an address on lines RA5– RA0
Note Both CS and MREQ must not be asserted concurrently If these signals are successively
asserted there must be at least two bus clocks between the deasserting edge of the first signal
and the asserting edge of the second signal
TABLE 2-1 Pin Description (Continued)
8
Description
CC
) selects Motorola mode (big