ISP1507EBS,518 NXP Semiconductors, ISP1507EBS,518 Datasheet - Page 16

• Manufacturer Part Number: ISP1507EBS,518
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507EBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285498518 ISP1507EBS-T

NXP Semiconductors
8. Modes of operation
Table 4.
ISP1507E_ISP1507F_1
Product data sheet
Signal name
CLOCK
DATA[3:0]
ULPI signal description
Direction on
ISP1507
I/O
I/O
8.1.1 Synchronous mode
8.1 ULPI modes
The ISP1507 ULPI bus can be programmed to operate in three modes. Each mode
reconfigures the signals on the data bus as described in the following subsections. Setting
more than one mode will lead to undefined behavior.
This is default mode. At power-up, and when CLOCK is stable, the ISP1507 will enter
synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the
set-up and hold times as defined in
synchronous mode is given in
This mode is used by the link to perform the following tasks:
For more information on the various synchronous mode protocols, see
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs)
Signal description
60 MHz interface clock. If a crystal is attached or a clock is driven into the XTAL1 pin, the
ISP1507 will drive a 60 MHz output clock.
4-bit data bus. In synchronous mode, the link drives DATA[3:0] to LOW by default. The link
initiates transfers by sending a nonzero data pattern called TXCMD (transmit command). In
synchronous mode, the direction of DATA[3:0] is controlled by DIR. Contents of DATA[3:0]
lines must be ignored for exactly one clock cycle whenever DIR changes value. This is called
the turnaround cycle. Bytes of data are transferred between the link and PHY in 4-bit nibbles.
The least significant nibble, DATA[3:0], is transferred first on the rising edge of clock. The
most significant nibble, DATA[7:4], is transferred next on the falling edge of clock. Transferring
an odd number of 4-bit nibbles is not allowed.
Data lines have fixed direction and different meaning in low-power and 3-pin serial modes.
Rev. 01 — 28 May 2008
Table
Section
4.
15. A description of the ULPI pin behavior in
ISP1507E; ISP1507F
ULPI HS USB OTG transceiver
© NXP B.V. 2008. All rights reserved.
Section
9.
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